5.16 Arbiter Request Mask Register
The arbiter request mask register contains the SERR enable on arbiter timeouts and the request mask controls. See
Table 5–14 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Arbiter request mask
R
0
R/W
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Arbiter request mask
Read-only, Read/Write
Offset:
Default:
62h
00h
Table 5–14. Arbiter Request Mask Register
BIT
TYPE
FUNCTION
7
R
Reserved. Bit 7 returns 0 when read.
Timeout automatic masking enable
6
5–4
3
R/W
R
0 = Masking not automatic (default)
1 = Allow masking after 16-clock timeout
Reserved. Bits 5 and 4 return 0s when read.
Request 3 (REQ3) mask bit
0 = Use request 3 (default)
1 = Ignore request 3
R/W
Request 2 (REQ2) mask bit
0 = Use request 2 (default)
1 = Ignore request 2
2
1
0
R/W
R/W
R/W
Request 1 (REQ1) mask bit
0 = Use request 1 (default)
1 = Ignore request 1
Request 0 (REQ0) mask bit
0 = Use request 0 (default)
1 = Ignore request 0
5–14
TI [ TEXAS INSTRUMENTS ]
