5.24 Power Management Control/Status Register
The power management control/status register determines and changes the current power state of the PCI2250. The
contents of this register are not affected by the internally generated reset caused by the transition from D3 to D0
hot
state. See Table 5–20 for a complete description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Power management control/status
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
Register:
Type:
Power management control/status
Read-only, Read/Write
Offset:
Default:
E0h
0000h
Table 5–20. Power Management Capabilities Register
BIT
TYPE
FUNCTION
15
R
R
PME status. This bit returns a 0 when read because the PCI2250 does not support PME.
Data scale. This two-bit read-only field indicates the scaling factor to be used when interpreting the value of the
data register. These bits return only 00b, because the data register is not implemented.
14–13
Data select. This four-bit field is used to select which data is to be reported through the data register and
data-scale field. These bits return only 0000b, because the data register is not implemented.
12–9
R
8
R
R
PME enable. This bit returns a 0 when read because the PCI2250 does not support PME signaling.
Reserved. Bits 7–2 return 0s when read.
7–2
Powerstate. Thistwo-bitfieldisusedbothtodeterminethecurrentpowerstateofafunctionandtosetthefunction
into a new power state. The definition of the two-bit field is given below:
00 – D0
01 – D1
10 – D2
1–0
R/W
11 – D3
hot
5–20
TI [ TEXAS INSTRUMENTS ]
