OMAP-L137 Low-Power Applications Processor
SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
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Table 6-58. General Timing Requirements for SPI1 Slave Modes (continued)
NO.
MIN
MAX UNIT
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5tc(SPC)S -3
Polarity = 0, Phase = 1,
from SPI1_CLK rising
0.5tc(SPC)S -3
Output hold time,
SPI1_SOMI valid after
receive edge of SPI1_CLK
14 toh(SPC_SOMI)S
ns
ns
ns
Polarity = 1, Phase = 0,
from SPI1_CLK rising
0.5tc(SPC)S -3
Polarity = 1, Phase = 1,
from SPI1_CLK falling
0.5tc(SPC)S -3
Polarity = 0, Phase = 0,
to SPI1_CLK falling
0
0
0
0
5
5
5
5
Polarity = 0, Phase = 1,
to SPI1_CLK rising
Input Setup Time,
SPI1_SIMO valid before
receive edge of SPI1_CLK
15 tsu(SIMO_SPC)S
Polarity = 1, Phase = 0,
to SPI1_CLK rising
Polarity = 1, Phase = 1,
to SPI1_CLK falling
Polarity = 0, Phase = 0,
from SPI1_CLK falling
Polarity = 0, Phase = 1,
from SPI1_CLK rising
Input Hold Time,
SPI1_SIMO valid after
receive edge of SPI1_CLK
16 tih(SPC_SIMO)S
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK falling
Table 6-59. Additional(1) SPI1 Master Timings, 4-Pin Enable Option(2)(3)
NO.
MIN
MAX UNIT
Polarity = 0, Phase = 0,
to SPI1_CLK rising
3P + 5
Polarity = 0, Phase = 1,
to SPI1_CLK rising
0.5tc(SPC)M + 3P + 5
Delay from slave assertion of
SPI1_ENA active to first
SPI1_CLK from master.(4)
17 td(EN A_SPC)M
ns
Polarity = 1, Phase = 0,
to SPI1_CLK falling
3P + 5
Polarity = 1, Phase = 1,
to SPI1_CLK falling
0.5tc(SPC)M + 3P + 5
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5tc(SPC)M
Polarity = 0, Phase = 1,
from SPI1_CLK falling
Max delay for slave to deassert
SPI1_ENA after final SPI1_CLK
edge to ensure master does not
begin the next transfer.(5)
0
0.5tc(SPC)M
0
18 td(SPC_ENA)M
ns
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK rising
(1) These parameters are in addition to the general timings for SPI master modes (Table 6-57).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI1_ENA assertion.
(5) In the case where the master SPI is ready with new data before SPI1_ENA deassertion.
156
Peripheral Information and Electrical Specifications
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