OMAP-L137 Low-Power Applications Processor
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SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
Table 6-60. Additional(1) SPI1 Master Timings, 4-Pin Chip Select Option(2)(3)
NO.
MIN
MAX UNIT
Polarity = 0, Phase = 0,
to SPI1_CLK rising
2P -3
Polarity = 0, Phase = 1,
to SPI1_CLK rising
0.5tc(SPC)M + 2P -3
Delay from SPI1_SCS active to
first SPI1_CLK(4)(5)
19 td(SCS_SPC)M
ns
Polarity = 1, Phase = 0,
to SPI1_CLK falling
2P -3
Polarity = 1, Phase = 1,
to SPI1_CLK falling
0.5tc(SPC)M + 2P -3
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5tc(SPC)M
Polarity = 0, Phase = 1,
from SPI1_CLK falling
0
0.5tc(SPC)M
0
Delay from final SPI1_CLK edge
20 td(SPC_SCS)M
to master deasserting SPI1_SCS
ns
(6)(7)
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK rising
(1) These parameters are in addition to the general timings for SPI master modes (Table 6-57).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI1_SCS assertion.
(5) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
(6) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI1_SCS will remain
asserted.
(7) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
Table 6-61. Additional(1) SPI1 Master Timings, 5-Pin Option(2)(3)
NO.
MIN
MAX UNIT
Polarity = 0, Phase = 0,
from SPI1_CLK falling
P + 5
Max delay for slave to
deassert SPI1_ENA after
final SPI1_CLK edge to
ensure master does not
begin the next
Polarity = 0, Phase = 1,
from SPI1_CLK falling
0.5tc(SPC)M + P + 5
18 td(SPC_ENA)M
ns
Polarity = 1, Phase = 0,
from SPI1_CLK rising
P + 5
transfer.(4)
Polarity = 1, Phase = 1,
from SPI1_CLK rising
0.5tc(SPC)M + P + 5
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5tc(SPC)M
Polarity = 0, Phase = 1,
from SPI1_CLK falling
Delay from final
0
0.5tc(SPC)M
0
SPI1_CLK edge to
master deasserting
20 td(SPC_SCS)M
ns
Polarity = 1, Phase = 0,
from SPI1_CLK rising
(5)(6)
SPI1_SCS
Polarity = 1, Phase = 1,
from SPI1_CLK rising
Max delay for slave SPI to drive SPI1_ENA valid
after master asserts SPI1_SCS to delay the
master from beginning the next transfer,
21 td(SCSL_ENAL)M
C2TDELAY + P ns
(1) These parameters are in addition to the general timings for SPI master modes (Table 6-58).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI1_ENA deassertion.
(5) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI1_SCS will remain
asserted.
(6) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
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