OMAP-L137 Low-Power Applications Processor
SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
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Table 6-61. Additional SPI1 Master Timings, 5-Pin Option (continued)
NO.
MIN
MAX UNIT
Polarity = 0, Phase = 0,
to SPI1_CLK rising
2P -3
Polarity = 0, Phase = 1,
to SPI1_CLK rising
0.5tc(SPC)M + 2P -3
2P -3
Delay from SPI1_SCS
active to first
22 td(SCS_SPC)M
ns
SPI1_CLK(7)(8)(9)
Polarity = 1, Phase = 0,
to SPI1_CLK falling
Polarity = 1, Phase = 1,
to SPI1_CLK falling
0.5tc(SPC)M + 2P -3
Polarity = 0, Phase = 0,
to SPI1_CLK rising
3P + 5
Polarity = 0, Phase = 1,
to SPI1_CLK rising
0.5tc(SPC)M + 3P + 5
3P + 5
Delay from assertion of
SPI1_ENA low to first
SPI1_CLK edge.(10)
23 td(ENA_SPC)M
ns
Polarity = 1, Phase = 0,
to SPI1_CLK falling
Polarity = 1, Phase = 1,
to SPI1_CLK falling
0.5tc(SPC)M + 3P + 5
(7) If SPI1_ENA is asserted immediately such that the transmission is not delayed by SPI1_ENA.
(8) In the case where the master SPI is ready with new data before SPI1_SCS assertion.
(9) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
(10) If SPI1_ENA was initially deasserted high and SPI1_CLK is delayed.
Table 6-62. Additional(1) SPI1 Slave Timings, 4-Pin Enable Option(2)(3)
NO.
MIN
MAX UNIT
Polarity = 0, Phase = 0,
1.5 P -3
2.5 P + 9.7
from SPI1_CLK falling
Polarity = 0, Phase = 1,
from SPI1_CLK falling
– 0.5tc(SPC)M + 1.5 P -3
1.5 P -3
– 0.5tc(SPC)M + 2.5 P + 9.7
2.5 P + 9.7
Delay from final
24 td(SPC_ENAH)S SPI1_CLK edge to slave
deasserting SPI1_ENA.
ns
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK rising
– 0.5tc(SPC)M + 1.5 P -3
– 0.5tc(SPC)M + 2.5 P + 9.7
(1) These parameters are in addition to the general timings for SPI slave modes (Table 6-58).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
Table 6-63. Additional(1) SPI1 Slave Timings, 4-Pin Chip Select Option(2)(3)
NO.
MIN
MAX UNIT
Required delay from SPI1_SCS asserted at slave to first
SPI1_CLK edge at slave.
25
td(SCSL_SPC)S
P
ns
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5tc(SPC)M + 0
Polarity = 0, Phase = 1,
0
0.5tc(SPC)M + 0
0
Required delay from final
from SPI1_CLK falling
26
td(SPC_SCSH)S
SPI1_CLK edge before
ns
Polarity = 1, Phase = 0,
SPI1_SCS is deasserted.
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK rising
Delay from master asserting SPI1_SCS to slave driving
SPI1_SOMI valid
27
28
tena(SCSL_SOMI)S
tdis(SCSH_SOMI)S
P + 9.7
P + 9.7
ns
ns
Delay from master deasserting SPI1_SCS to slave 3-stating
SPI1_SOMI
(1) These parameters are in addition to the general timings for SPI slave modes (Table 6-58).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
158
Peripheral Information and Electrical Specifications
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