OMAP-L137 Low-Power Applications Processor
SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
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Table 6-53. Additional(1) SPI0 Master Timings, 5-Pin Option(2)(3)
NO.
MIN
MAX UNIT
Polarity = 0, Phase = 0,
from SPI0_CLK falling
P + 5
Max delay for slave to
deassert SPI0_ENA after
final SPI0_CLK edge to
ensure master does not
begin the next
Polarity = 0, Phase = 1,
from SPI0_CLK falling
0.5tc(SPC)M + P + 5
18 td(SPC_ENA)M
ns
Polarity = 1, Phase = 0,
from SPI0_CLK rising
P + 5
transfer.(4)
Polarity = 1, Phase = 1,
from SPI0_CLK rising
0.5tc(SPC)M + P + 5
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5tc(SPC)M
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Delay from final
0
0.5tc(SPC)M
0
SPI0_CLK edge to
master deasserting
20 td(SPC_SCS)M
21 td(SCSL_ENAL)M
22 td(SCS_SPC)M
ns
Polarity = 1, Phase = 0,
from SPI0_CLK rising
(5)(6)
SPI0_SCS
Polarity = 1, Phase = 1,
from SPI0_CLK rising
Max delay for slave SPI to drive SPI0_ENA valid
after master asserts SPI0_SCS to delay the
master from beginning the next transfer,
C2TDELAY + P ns
Polarity = 0, Phase = 0,
to SPI0_CLK rising
2P -3
0.5tc(SPC)M + 2P -3
2P -3
Polarity = 0, Phase = 1,
Delay from SPI0_SCS
to SPI0_CLK rising
active to first
ns
SPI0_CLK(7)(8)(9)
Polarity = 1, Phase = 0,
to SPI0_CLK falling
Polarity = 1, Phase = 1,
to SPI0_CLK falling
0.5tc(SPC)M + 2P -3
Polarity = 0, Phase = 0,
to SPI0_CLK rising
3P + 5
Polarity = 0, Phase = 1,
0.5tc(SPC)M + 3P + 5
Delay from assertion of
to SPI0_CLK rising
23 td(ENA_SPC)M
SPI0_ENA low to first
ns
SPI0_CLK edge.(10)
Polarity = 1, Phase = 0,
to SPI0_CLK falling
3P + 5
Polarity = 1, Phase = 1,
to SPI0_CLK falling
0.5tc(SPC)M + 3P + 5
(1) These parameters are in addition to the general timings for SPI master modes (Table 6-50).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI0_ENA deassertion.
(5) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI0_SCS will remain
asserted.
(6) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
(7) If SPI0_ENA is asserted immediately such that the transmission is not delayed by SPI0_ENA.
(8) In the case where the master SPI is ready with new data before SPI0_SCS assertion.
(9) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
(10) If SPI0_ENA was initially deasserted high and SPI0_CLK is delayed.
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Peripheral Information and Electrical Specifications
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