OMAP-L137 Low-Power Applications Processor
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SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
Table 6-54. Additional(1) SPI0 Slave Timings, 4-Pin Enable Option(2)(3)
NO.
MIN
MAX UNIT
2.5 P + 9
Polarity = 0, Phase = 0,
from SPI0_CLK falling
1.5 P -3
– 0.5tc(SPC)M + 1.5 P -3
1.5 P -3
Polarity = 0, Phase = 1,
from SPI0_CLK falling
– 0.5tc(SPC)M + 2.5 P + 9
2.5 P + 9
Delay from final
24 td(SPC_ENAH)S SPI0_CLK edge to slave
deasserting SPI0_ENA.
ns
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK rising
– 0.5tc(SPC)M + 1.5 P -3
– 0.5tc(SPC)M + 2.5 P + 9
(1) These parameters are in addition to the general timings for SPI slave modes (Table 6-50).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
Table 6-55. Additional(1) SPI0 Slave Timings, 4-Pin Chip Select Option(2)(3)
NO.
MIN
MAX UNIT
Required delay from SPI0_SCS asserted at slave to first
SPI0_CLK edge at slave.
25
td(SCSL_SPC)S
P
ns
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5tc(SPC)M + 0
Polarity = 0, Phase = 1,
0
0.5tc(SPC)M + 0
0
Required delay from final
from SPI0_CLK falling
26
td(SPC_SCSH)S
SPI0_CLK edge before
ns
Polarity = 1, Phase = 0,
SPI0_SCS is deasserted.
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK rising
Delay from master asserting SPI0_SCS to slave driving
SPI0_SOMI valid
27
28
tena(SCSL_SOMI)S
tdis(SCSH_SOMI)S
P + 9
P + 9
ns
ns
Delay from master deasserting SPI0_SCS to slave 3-stating
SPI0_SOMI
(1) These parameters are in addition to the general timings for SPI slave modes (Table 6-50).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
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Peripheral Information and Electrical Specifications
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