OMAP-L137 Low-Power Applications Processor
SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
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Table 6-56. Additional(1) SPI0 Slave Timings, 5-Pin Option(2)(3)
NO.
MIN
MAX UNIT
Required delay from SPI0_SCS asserted at slave to first
SPI0_CLK edge at slave.
25
td(SCSL_SPC)S
P
ns
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5tc(SPC)M + 0
Polarity = 0, Phase = 1,
0
0.5tc(SPC)M + 0
0
Required delay from final
from SPI0_CLK falling
26
td(SPC_SCSH)S
SPI0_CLK edge before
ns
Polarity = 1, Phase = 0,
SPI0_SCS is deasserted.
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK rising
Delay from master asserting SPI0_SCS to slave driving
SPI0_SOMI valid
27
28
29
tena(SCSL_SOMI)S
tdis(SCSH_SOMI)S
tena(SCSL_ENA)S
P + 9
P + 9
ns
ns
ns
Delay from master deasserting SPI0_SCS to slave 3-stating
SPI0_SOMI
Delay from master deasserting SPI0_SCS to slave driving
SPI0_ENA valid
9
Polarity = 0, Phase = 0,
from SPI0_CLK falling
2.5 P + 9
2.5 P + 9
2.5 P + 9
2.5 P + 9
Polarity = 0, Phase = 1,
from SPI0_CLK rising
Delay from final clock receive
edge on SPI0_CLK to slave
3-stating or driving high
SPI0_ENA.(4)
30
tdis(SPC_ENA)S
ns
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK falling
(1) These parameters are in addition to the general timings for SPI slave modes (Table 6-50).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
(4) SPI0_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to 0. Otherwise it is
tri-stated. If tri-stated, an external pullup resistor should be used to provide a valid level to the master. This option is useful when tying
several SPI slave devices to a single master.
Table 6-57. General Timing Requirements for SPI1 Master Modes(1)
NO.
1
MIN
greater of 2P or 20 ns
0.5tc(SPC)M - 1
MAX UNIT
tc(SPC)M
Cycle Time, SPI1_CLK, All Master Modes
Pulse Width High, SPI1_CLK, All Master Modes
Pulse Width Low, SPI1_CLK, All Master Modes
256P ns
2
tw(SPCH)M
tw(SPCL)M
ns
ns
3
0.5tc(SPC)M - 1
Polarity = 0, Phase = 0,
to SPI1_CLK rising
5
0.5tc(SPC)M - 5
5
Polarity = 0, Phase = 1,
Delay, initial data bit valid
to SPI1_CLK rising
4,5 td(SIMO_SPC)M
on SPI1_SIMO to initial
ns
edge on SPI1_CLK(2)
Polarity = 1, Phase = 0,
to SPI1_CLK falling
Polarity = 1, Phase = 1,
to SPI1_CLK falling
0.5tc(SPC)M - 5
Polarity = 0, Phase = 0,
from SPI1_CLK rising
5
Polarity = 0, Phase = 1,
5
Delay, subsequent bits
from SPI1_CLK falling
5
td(SPC_SIMO)M
valid on SPI1_SIMO after
ns
5
Polarity = 1, Phase = 0,
from SPI1_CLK falling
transmit edge of SPI1_CLK
Polarity = 1, Phase = 1,
from SPI1_CLK rising
5
(1) P = SYSCLK2 period
(2) First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on
SPI1_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPI1_SOMI.
154
Peripheral Information and Electrical Specifications
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