OMAP-L137 Low-Power Applications Processor
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SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
Table 6-64. Additional(1) SPI1 Slave Timings, 5-Pin Option(2)(3)
NO.
MIN
MAX UNIT
Required delay from SPI1_SCS asserted at slave to first
SPI1_CLK edge at slave.
25
td(SCSL_SPC)S
P
ns
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5tc(SPC)M + 0
Polarity = 0, Phase = 1,
from SPI1_CLK falling
0
0.5tc(SPC)M + 0
0
Required delay from final
SPI1_CLK edge before
SPI1_SCS is deasserted.
26
td(SPC_SCSH)S
ns
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK rising
Delay from master asserting SPI1_SCS to slave driving
SPI1_SOMI valid
27
28
29
tena(SCSL_SOMI)S
tdis(SCSH_SOMI)S
tena(SCSL_ENA)S
P + 9.7
ns
ns
ns
Delay from master deasserting SPI1_SCS to slave 3-stating
SPI1_SOMI
P + 9.7
9.7
Delay from master deasserting SPI1_SCS to slave driving
SPI1_ENA valid
Polarity = 0, Phase = 0,
from SPI1_CLK falling
2.5 P + 9.7
2.5 P + 9.7
2.5 P + 9.7
2.5 P + 9.7
Polarity = 0, Phase = 1,
from SPI1_CLK rising
Delay from final clock receive
edge on SPI1_CLK to slave
3-stating or driving high
SPI1_ENA.(4)
30
tdis(SPC_ENA)S
ns
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK falling
(1) These parameters are in addition to the general timings for SPI slave modes (Table 6-58).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
(4) SPI1_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to 0. Otherwise it is
tri-stated. If tri-stated, an external pullup resistor should be used to provide a valid level to the master. This option is useful when tying
several SPI slave devices to a single master.
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Peripheral Information and Electrical Specifications
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