OMAP-L137 Low-Power Applications Processor
SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
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Table 6-50. General Timing Requirements for SPI0 Slave Modes(1)
NO.
MIN
MAX UNIT
greater of 2P or
20 ns
9
tc(SPC)S
Cycle Time, SPI0_CLK, All Slave Modes
256P ns
10 tw(SPCH)S
11 tw(SPCL)S
Pulse Width High, SPI0_CLK, All Slave Modes
Pulse Width Low, SPI0_CLK, All Slave Modes
10
10
ns
ns
Polarity = 0, Phase = 0,
to SPI0_CLK rising
2P
2P
2P
2P
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Setup time, transmit data
written to SPI before initial
clock edge from
12 tsu(SOMI_SPC)S
13 td(SPC_SOMI)S
14 toh(SPC_SOMI)S
15 tsu(SIMO_SPC)S
ns
Polarity = 1, Phase = 0,
to SPI0_CLK falling
master.(2)(3)
Polarity = 1, Phase = 1,
to SPI0_CLK falling
Polarity = 0, Phase = 0,
from SPI0_CLK rising
9
Polarity = 0, Phase = 1,
from SPI0_CLK falling
9
Delay, subsequent bits
valid on SPI0_SOMI after
transmit edge of SPI0_CLK
ns
9
Polarity = 1, Phase = 0,
from SPI0_CLK falling
Polarity = 1, Phase = 1,
from SPI0_CLK rising
9
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5tc(SPC)S -3
Polarity = 0, Phase = 1,
from SPI0_CLK rising
0.5tc(SPC)S -3
Output hold time,
SPI0_SOMI valid after
receive edge of SPI0_CLK
ns
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5tc(SPC)S -3
Polarity = 1, Phase = 1,
from SPI0_CLK falling
0.5tc(SPC)S -3
Polarity = 0, Phase = 0,
to SPI0_CLK falling
0
0
0
0
5
5
5
5
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Input Setup Time,
SPI0_SIMO valid before
receive edge of SPI0_CLK
ns
Polarity = 1, Phase = 0,
to SPI0_CLK rising
Polarity = 1, Phase = 1,
to SPI0_CLK falling
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Polarity = 0, Phase = 1,
from SPI0_CLK rising
Input Hold Time,
SPI0_SIMO valid after
receive edge of SPI0_CLK
16 tih(SPC_SIMO)S
ns
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK falling
(1) P = SYSCLK2 period
(2) First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on
SPI0_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPI0_SIMO.
(3) Measured from the termination of the write of new data to the SPI module, In analyzing throughput requirements, additional internal bus
cycles must be accounted for to allow data to be written to the SPI module by the DSP CPU.
150
Peripheral Information and Electrical Specifications
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