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DRV8301-Q1 参数 Datasheet PDF下载

DRV8301-Q1图片预览
型号: DRV8301-Q1
PDF下载: 下载PDF文件 查看货源
内容描述: 汽车三相预驱动器,带有双电流分流放大器 [AUTOMOTIVE THREE PHASE PRE-DRIVER WITH DUAL CURRENT SHUNT AMPLIFIERS]
分类和应用: 驱动器放大器
文件页数/大小: 28 页 / 413 K
品牌: TI [ TEXAS INSTRUMENTS ]
 浏览型号DRV8301-Q1的Datasheet PDF文件第4页浏览型号DRV8301-Q1的Datasheet PDF文件第5页浏览型号DRV8301-Q1的Datasheet PDF文件第6页浏览型号DRV8301-Q1的Datasheet PDF文件第7页浏览型号DRV8301-Q1的Datasheet PDF文件第9页浏览型号DRV8301-Q1的Datasheet PDF文件第10页浏览型号DRV8301-Q1的Datasheet PDF文件第11页浏览型号DRV8301-Q1的Datasheet PDF文件第12页  
DRV8301-Q1  
SLOS842 SEPTEMBER 2013  
www.ti.com  
MAX UNIT  
ELECTRICAL CHARACTERISTICS (continued)  
PVDD = 6 V to 60 V, TC = 25°C, unless specified under test condition  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
GATE DRIVE OUTPUT: GH_A, GH_B, GH_C, GL_A, GL_B, GL_C  
PVDD = 8V–60V, Igate = 30mA,  
CCP = 22nF  
9.5  
9.5  
8.8  
8.3  
11.5  
V
VGX_NORM Gate driver Vgs voltage  
PVDD = 8V–60V, Igate = 30mA,  
CCP = 220nF  
11.5  
PVDD = 6V–8V, Igate = 15mA,  
CCP = 22nF  
VGX_MIN  
Gate driver Vgs voltage  
V
PVDD = 6V–8V, Igate = 30mA,  
CCP = 220nF  
Ioso1  
Iosi1  
Ioso2  
Iosi2  
Ioso3  
Iosi3  
Maximum source current setting 1, peak  
Maximum sink current setting 1, peak  
Source current setting 2, peak  
Sink current setting 2, peak  
Vgs of FET equals to 2 V. REG 0x02  
Vgs of FET equals to 8 V. REG 0x02  
Vgs of FET equals to 2 V. REG 0x02  
Vgs of FET equals to 8 V. REG 0x02  
Vgs of FET equals to 2 V. REG 0x02  
Vgs of FET equals to 8 V. REG 0x02  
1.7  
2.3  
0.7  
1
A
A
A
A
A
A
Source current setting 3, peak  
Sink current setting 3, peak  
0.25  
0.5  
Gate output impedence during standby mode  
when EN_GATE low (pins GH_x, GL_x)  
Rgate_off  
1.6  
2.4  
50  
kΩ  
SUPPLY CURRENTS  
IPVDD1_STB PVDD1 supply current, standby  
EN_GATE is low. PVDD1 = 8V.  
20  
15  
5
µA  
mA  
mA  
EN_GATE is high, no load on gate drive  
output, switching at 10 kHz,  
100 nC gate charge  
IPVDD1_OP PVDD1 supply current, operating  
IPVDD1_HIZ PVDD1 Supply current, HiZ  
EN_GATE is high, gate not switching  
2
10  
INTERNAL REGULATOR VOLTAGE  
PVDD = 8V - 60V  
PVDD = 6V - 60V  
6
5.5  
3
6.5  
3.3  
7
6
AVDD  
DVDD  
AVDD voltage  
DVDD voltage  
V
V
3.6  
VOLTAGE PROTECTION  
PVDD falling  
PVDD rising  
GVDD falling  
5.9  
6
VPVDD_UV  
Under voltage protection limit, PVDD  
V
VGVDD_UV Under voltage protection limit, GVDD  
VGVDD_OV Over voltage protection limit, GVDD  
CURRENT PROTECTION, (VDS SENSING)  
7.5  
V
V
16  
PVDD = 8V - 60V  
PVDD = 6V - 8V(1)  
0.125  
0.125  
2.4  
VDS_OC  
Drain-source voltage protection limit  
OC sensing response time  
V
1.491  
Toc  
1.5  
64  
µs  
µs  
OCTW pin reporting pulse stretch length for OC  
event  
TOC_PULSE  
(1) Reduced AVDD voltage range results in limitations on settings for over current protection. See Table 10.  
8
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Copyright © 2013, Texas Instruments Incorporated  
Product Folder Links: DRV8301-Q1  
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