DRV8301-Q1
SLOS842 –SEPTEMBER 2013
www.ti.com
Table 1. Fault and Warning Reporting and Handling
REPORTING ON REPORTING ON
REPORTING IN SPI
STATUS REGISTER
EVENT
ACTION
LATCH
FAULT PIN
OCTW PIN
External FETs HiZ;
Weak pull down of all gate
driver output
PVDD
undervoltage
N
Y
N
Y
External FETs HiZ;
DVDD
undervoltage
Weak pull down of all gate
driver output; When recovering,
reset all status registers
N
N
Y
Y
N
N
N
Y
External FETs HiZ;
Weak pull down of all gate
driver output
GVDD
undervoltage
External FETs HiZ;
Weak pull down of all gate driver
output
Shut down the charge pump
Won’t recover and reset through
SPI reset command or
GVDD
overvoltage
Y
Y
N
Y
quick EN_GATE toggling
Y (in default
setting)
OTW
None
N
Y
N
Y
Y
Y
Gate driver latched shut down.
Weak pull down of all gate driver
output
to force external FETs HiZ
Shut down the charge pump
OTSD_GATE
OTSD_BUCK
Y
OTSD of Buck
Y
N
N
N
N
N
N
Buck output
undervoltage
UVLO_BUCK: auto-restart
Y, in PWRGD pin
Buck current limiting
Buck overload
External FET
overload – current
limit mode
(HiZ high side until current reaches
zero and then auto-recovering)
N
N
N
N
N
Y
N
External FETs current Limiting
(only OC detected FET)
Y, indicates which phase
has OC
Weak pull down of gate driver
output and PWM logic “0” of
LS and HS in the same phase.
External FETs HiZ
External FET
overload – Latch
mode
Y
N
Y
N
Y
Y
Y
External FET
Y, indicates which phase
has OC
overload –
reporting only
mode
Reporting only
16
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: DRV8301-Q1
TI [ TEXAS INSTRUMENTS ]
