ADS131B04-Q1
ZHCSMK3B –NOVEMBER 2020 –REVISED NOVEMBER 2021
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8.6.1 ID Register (Address = 00h) [reset = 44xxh]
The ID register is shown in 图8-26 and described in 表8-13.
Return to the Summary Table.
图8-26. ID Register
15
14
13
12
11
10
CHANCNT[3:0]
R-0100b
9
1
8
0
RESERVED
R-0100b
7
6
5
4
3
2
RESERVED
R-xxxxxxxxb
表8-13. ID Register Field Descriptions
Bit
Field
RESERVED
Type
Reset
Description
15:12
11:8
7:0
R
0100b
Reserved
Always reads 0100b
CHANCNT[3:0]
RESERVED
R
R
0100b
Channel count
Always reads 0100b
xxxxxxxxb
Reserved
Values are subject to change without notice
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