ADS131B04-Q1
ZHCSMK3B –NOVEMBER 2020 –REVISED NOVEMBER 2021
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8.6.2 STATUS Register (Address = 01h) [reset = 0500h]
The STATUS register is shown in 图8-27 and described in 表8-14.
Return to the Summary Table.
图8-27. STATUS Register
15
14
13
12
11
10
9
1
8
LOCK
R-0b
F_RESYNC
R-0b
REG_MAP
R-0b
CRC_ERR
R-0b
CRC_TYPE
R-0b
RESET
R-1b
WLENGTH[1:0]
R-01b
7
6
5
4
3
2
0
RESERVED
R-0000b
DRDY3
R-0b
DRDY2
R-0b
DRDY1
R-0b
DRDY0
R-0b
表8-14. STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
15
LOCK
R
0b
SPI interface lock indicator
0b = Unlocked
1b = Locked
14
F_RESYNC
R
0b
ADC resynchronization indicator
Bit is set each time the ADC resynchronizes.
0b = No resynchronization
1b = Resynchronization occurred
13
12
11
REG_MAP
CRC_ERR
CRC_TYPE
RESET
R
R
R
R
R
0b
0b
0b
1b
01b
Register map CRC fault indicator
0b = No change in the register map CRC
1b = register map CRC changed
SPI input CRC error indicator
0b = No CRC error
1b = Input CRC error occured
CRC type indicator
0b = 16 bit CCITT
1b = 16 bit ANSI
10
9:8
Reset status indicator
0b = No reset occurred
1b = Reset occurred
WLENGTH[1:0]
Data word length indicator
00b = 16 bit
01b = 24 bits
10b = 32 bits: LSB zero padding
11b = 32 bits: MSB sign extension
7:4
3
RESERVED
DRDY3
R
R
0000b
0b
Reserved
Always reads 0000b
Channel 3 ADC data available indicator
0b = No new data available
1b = New data available
2
1
0
DRDY2
DRDY1
DRDY0
R
R
R
0b
0b
0b
Channel 2 ADC data available indicator
0b = No new data available
1b = New data available
Channel 1 ADC data available indicator
0b = No new data available
1b = New data available
Channel 0 ADC data available indicator
0b = No new data available
1b = New data available
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