ADS131B04-Q1
ZHCSMK3B –NOVEMBER 2020 –REVISED NOVEMBER 2021
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表8-11. Register Map (continued)
BIT 15
BIT 7
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 2
BIT 9
BIT 1
BIT 8
BIT 0
RESET
VALUE
ADDRESS
REGISTER
BIT 6
BIT 5
BIT 4
BIT 3
GCAL2_MSB[15:8]
16h
CH2_GCAL_MSB
CH2_GCAL_LSB
CH3_CFG
8000h
0000h
0000h
0000h
0000h
8000h
0000h
GCAL2_MSB[7:0]
GCAL2_LSB[7:0]
RESERVED
17h
18h
19h
1Ah
1Bh
1Ch
RESERVED
RESERVED
MUX3[1:0]
OCAL3_MSB[15:8]
OCAL3_MSB[7:0]
OCAL3_LSB[7:0]
RESERVED
CH3_OCAL_MSB
CH3_OCAL_LSB
CH3_GCAL_MSB
CH3_GCAL_LSB
GCAL3_MSB[15:8]
GCAL3_MSB[7:0]
GCAL3_LSB[7:0]
RESERVED
REGISTER MAP CRC AND RESERVED REGISTERS
REG_CRC[15:8]
REG_CRC[7:0]
RESERVED
3Eh
3Fh
REGMAP_CRC
RESERVED
0000h
0000h
RESERVED
表8-12 shows the codes that are used for access types in this section.
表8-12. Access Type Codes
Access Type
Code
Description
Read Type
R
R
Read
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default value
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