ADS131B04-Q1
ZHCSMK3B –NOVEMBER 2020 –REVISED NOVEMBER 2021
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图 8-24 shows an example of how to collect data after a period of the ADC running, but where no data are being
retrieved. In this instance, the SYNC/RESET pin is used to clear the internal FIFOs and realign the ADS131B04-
Q1 output data with the host.
Time where data is
not being read
DRDY
SYNC / RESET
SYNC Pulse
CS
SCLK
Hi-Z
DOUT
Data
Data
CRC
Status
Data
CRC
图8-24. Collecting Data After a Pause in Data Collection Using the SYNC/RESET Pin
Another functionally equivalent method for clearing the FIFO after a pause in collecting data is to begin by
reading two samples in quick succession. 图 8-25 depicts this method. There is a very narrow pulse on DRDY
immediately after the first set of data are shifted out of the device. This pulse may be too narrow for some
microcontrollers to detect. Therefore, do not rely upon this pulse, but instead immediately read out the second
data set after the first data set. DRDY transitions high after the second data set is read, which indicates that no
other new data are available for readout.
Time where data is
not being read
Narrow DRDY Pulse
DRDY
CS
SCLK
Hi-Z
DOUT
Data
Data
CRC
Status
Data
CRC
Status
Data
CRC
Data is read a
second time
图8-25. Collecting Data After a Pause in Data Collection by Reading Data Twice
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