ADS131B04-Q1
ZHCSMK3B –NOVEMBER 2020 –REVISED NOVEMBER 2021
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8.6.5 GAIN Register (Address = 04h) [reset = 0000h]
The GAIN register is shown in 图8-30 and described in 表8-17.
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图8-30. GAIN Register
15
14
13
12
11
10
2
9
8
0
RESERVED
R/W-0b
PGAGAIN3[2:0]
R/W-000b
RESERVED
R/W-0b
PGAGAIN2[2:0]
R/W-000b
7
6
5
4
3
1
RESERVED
R/W-0b
PGAGAIN1[2:0]
R/W-000b
RESERVED
R/W-0b
PGAGAIN0[2:0]
R/W-000b
表8-17. GAIN Register Field Descriptions
Bit
Field
Type
Reset
Description
15
RESERVED
R/W
0b
Reserved
Always write 0b
14:12
PGAGAIN3[2:0]
R/W
000b
PGA gain selection for channel 3
000b = 1
001b = 2
010b = 4
011b = 8
100b = 16
101b = 32
110b = 64
111b = 128
11
RESERVED
R/W
R/W
0b
Reserved
Always write 0b
10:8
PGAGAIN2[2:0]
000b
PGA gain selection for channel 2
000b = 1
001b = 2
010b = 4
011b = 8
100b = 16
101b = 32
110b = 64
111b = 128
7
RESERVED
R/W
R/W
0b
Reserved
Always write 0b
6:4
PGAGAIN1[2:0]
000b
PGA gain selection for channel 1
000b = 1
001b = 2
010b = 4
011b = 8
100b = 16
101b = 32
110b = 64
111b = 128
3
RESERVED
R/W
R/W
0b
Reserved
Always write 0b
2:0
PGAGAIN0[2:0]
000b
PGA gain selection for channel 0
000b = 1
001b = 2
010b = 4
011b = 8
100b = 16
101b = 32
110b = 64
111b = 128
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