DS_8430_001
78Q8430 Data Sheet
Address: 0x1E8
Name: HIR
Reset Val: 0x0000_0000
Block: CTL
Bits
6
Type
Default Description
RO
RO
0
0
Reserved.
5
Late Tx Notify
Interrupt on completion. (See PCWR)
4
3
2
1
0
RO
RO
RO
RO
RO
0
0
0
0
0
Early Tx Notify
Interrupt at the start of transmission. (See PCWR)
WATER MARK
Interrupt when the free BLOCK count hits the low water mark.
QUE Overflow
Interrupt when a QUE requests memory and there is none.
PAUSE
Interrupt when the local pause changes state (on/off).
Class
Packet classification interrupt.
Note: Bits 15:0 are cleared on read. Bits 31:16 are only cleared when the source is cleared.
7.6.42 Host Interrupt Mask Register
Name: HIMR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x1EC
Bits
Type
RW
Default Description
Host Interrupt Mask
31:0
When a bit is set here it enables the host interrupt for the corresponding
bit in the HIR. When a bit is clear here, the corresponding bit in the HIR
will still be set on its event and cleared on read but will not trigger an
interrupt on INT.
Rev. 1.2
73
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
