78Q8430 Data Sheet
DS_8430_001
7.6.38 Transmit RMON Mask Register
Name: TRMR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x1D4
Bits
Type
RW
Default Description
31:0
0x0000 Tx RMON Interrupt Mask
0000
When a bit is set, it enables the Tx RMON interrupt for the
corresponding bit in the TRIR. When a bit is clear, the corresponding
bit in the TRIR will still be set on its event and cleared on read but will
not be passed on to the HIR.
7.6.39 Receive RMON Interrupt Register
Name: RRIR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x1D8
Bits
Type
RO
Default Description
31:0
0x0000 RMON Rx Counter Rollover
0000
Set when the RMON Rx counter with an index equal to the bit number
plus 32 has rolled over.
Note: All bits are cleared on read.
7.6.40 Receive RMON Mask Register
Name: RRMR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x1DC
Bits
Type
RW
Default Description
31:0
0x0000 Rx RMON Interrupt Mask
0000
When a bit is set, it enables the Rx RMON interrupt for the
corresponding bit in the RRIR. When a bit is clear, the corresponding
bit in the RRIR will still be set on its event and cleared on read but will
not be passed on to the HIR.
7.6.41 Host Interrupt Register
Name: HIR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x1E8
Bits
31:21
20
Type
X
Default Description
0x000
0
Reserved
RO
WAKE
PME is asserted low (a power event has occurred).
19
18
RO
RO
0
0
QUE Status
QSIR interrupt.
QUE Overflow/Underrun
OUIR interrupt.
17
RO
RO
X
0
0
0
0
PHY
16
RMON
Reserved
15:13
12
RO
Tx Bad
A transmitted frame had an error.
11
RO
0
Rx Bad
A frame was received with an error.
Reserved
10:9
8
X
RO
0
0
Late Rx Notify
This interrupt is asserted each time an entire frame is added to the
receive QUE.
7
RO
Early Rx Notify
Data reception has started (delayed by the IDCR).
72
Rev. 1.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
