DS_8430_001
78Q8430 Data Sheet
7.7.2 PHY Control Register – MR0
Bits
Symbol
Type Default Description
15
RESET
R/WC
0
Reset
Setting this bit to 1 resets the device and sets all registers to
the default states. This bit is self-clearing.
14
13
LOOPBK
R/W
0
Loopback
When this bit is set to 1, input data at TXD[3:0] is output at
RXD[3:0]. No transmission of data on the network medium
occurs and receive data on the network medium is ignored.
By default, the loopback signal path encompasses most of the
digital functional blocks. This bit allows for diagnostic testing.
SPEEDSL
R/W
1
Speed Selection
This bit determines the speed of operation of the 78Q8430
PHY. Setting this bit to 1 indicates 100Base-TX operation and
a 0 indicates 10Base-T mode. This bit will default to 1 upon
reset. When auto-negotiation is enabled, this bit will not be
writable and will have no effect on the 78Q8430 PHY. If
auto-negotiation is not enabled, this bit may be written to force
manual configuration.
12
11
ANEGEN
PWRDN
R/W
R/W
1
0
Auto-negotiation Enable
The auto-negotiation process is enabled by setting this bit to 1.
This bit will default to 1. If this bit is cleared to 0, manual speed
and duplex mode selection is accomplished through bit 13
(SPEEDSL) and bit 8 (DUPLEX) of the MR0 Control Register.
Power-down
The device may be placed in a low power consumption state
by setting this bit to 1. While in the power-down state, the
device will still respond to management transactions.
10
9
RSVD
R
0
0
Reserved
RANEG
R/WC
Restart Auto-negotiation
Normally, the Auto-Negotiation process is started at power up.
The process can be restarted by setting this bit to 1. This bit
is self-clearing.
8
DUPLEX
R/W
1
Duplex Mode
This bit determines whether the device supports full- duplex or
half duplex. A 1 indicates full duplex operation and a 0
indicates half duplex. This bit will default to 1 upon reset.
When auto-negotiation is enabled, this bit will not be writable
and will have no effect on the 78Q8430 PHY. If
auto-negotiation is not enabled, this bit may be written to force
manual configuration.
7
COLT
RSVD
R/W
0
0
Collision Test
When this bit is set to 1, the device will assert the COL signal
in response to the assertion of the TX_EN signal. Collision
test is disabled if the PCSBP bit, MR16[1], is high. The
Collision test can be activated regardless of the duplex mode
of operation.
6:0
R
Reserved
Rev. 1.2
75
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
