DS_8430_001
78Q8430 Data Sheet
Bits
Symbol
Type Default Description
1
JAB
RC/LH
0
Jabber Detect
In 10Base-T mode, this bit is set during a jabber event. After
the event, the bit remains set until cleared by a read operation.
0
EXTD
R
1
Extended Capability
Reads 1 to indicate the 78Q8430 PHY provides an extended
register set (MR2 and beyond).
7.7.4 PHY Identifier Registers – MR2, MR3
MR2: PHY Identifier Register 1
Bits
15:0
Symbol
OUI
Type
R
Value Description
000Eh Organizationally Unique Identifier
This value is 00-C0-39 for Teridian Semiconductor Corporation.
This register contains 16 of the upper 18 bits of the identifier.
[23:6]
MR3: PHY Identifier Register 2
Bits
15:10
Symbol
OUI
Type
R
Value Description
1Ch Organizationally Unique Identifier
The remaining 6 bits of the 24-bit OUI.
[5:0]
9:4
3:0
MN
R
R
23h
03h
Model Number
The 23 from the model number is encoded into the 6 bits.
RN
Revision Number
The value 0011 corresponds to the third revision of the silicon.
7.7.5 PHY Auto-Negotiation Advertisement Registers – MR4
Bits
Symbol
Type Default Description
15
NP
R
0
Next Page
Not supported. Reads logic zero.
14
13
RSVD
RF
R
0
0
Reserved
R/W
Remote Fault
Setting this bit to 1 allows the device to indicate to the link
partner a Remote Fault Condition.
12:5
TAF
R/W
(0Fh) Technology Ability Field
The default value of this field is dependent upon the MR1.15:
11 register bits. This field can be overwritten by management
to auto-negotiate to an alternate common technology. Writing
to this register has no effect until auto-negotiation is re-initiated.
12
11
A7
R
0
0
Reserved
ASYMP
R/W
Asymmetric PAUSE Operation for Full Duplex Links
0 = Asymmetric PAUSE operation not supported
1 = Asymmetric PAUSE operation is supported
Writing to this register has no effect until auto-negotiation is
re-initiated.
10
PAUSE
R/W
0
PAUSE Operation for Full Duplex Links
0 = PAUSE operation not supported
1 = PAUSE operation is supported
Writing to this register has no effect until auto-negotiation is
re-initiated.
9
8
A4
A3
R
0
1
100BASE-T4
The 78Q8430 PHY does not support 100BASE-T4 operations.
100BASE-TX Full Duplex
R/W
This bit will be set to 1 upon reset and is writeable. Writing to
this register has no effect until auto-negotiation is re-initiated.
Rev. 1.2
77
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
