DS_8430_001
78Q8430 Data Sheet
7.6.35 Overflow/Underrun Interrupt Register
Name: OUIR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x1C8
Bits
Type
Default Description
31
RO
0
QUE Data Overflow
Overflow condition detected on QUE 7.
30
RO
0
QUE Data Underrun
Under-run condition detected on QUE 7.
29:28
27:26
RO
RO
00
Reserved
0x0
QUE 6
QUE Data Overflow and QUE Data Underrun bits for QUE 6.
25:24
23:22
RO
RO
00
Reserved
0x0
QUE 5
QUE Data Overflow and QUE Data Underrun bits for QUE 5.
21:20
19:18
RO
RO
00
Reserved
0x0
QUE 4
QUE Data Overflow and QUE Data Underrun bits for QUE 4.
17:16
15:14
RO
RO
00
Reserved
0x0
QUE 3
QUE Data Overflow and QUE Data Underrun bits for QUE 3.
13:12
11:10
RO
RO
00
Reserved
0x0
QUE 2
QUE Data Overflow and QUE Data Underrun bits for QUE 2.
9:8
7:6
RO
RO
00
Reserved
0x0
QUE 1
QUE Data Overflow and QUE Data Underrun bits for QUE 1.
5:4
3:2
RO
RO
00
Reserved
0x0
QUE 0
QUE Data Overflow and QUE Data Underrun bits for QUE 0.
1:0
RO
00
Reserved
Note: All bits are cleared on read.
7.6.36 Overflow/Underrun Mask Register
Name: OUMR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x1CC
Bits
Type
RW
Default Description
31:0
0x0000 Overflow/Underrun Interrupt Mask
0000
When a bit is set, it enables the overflow/underrun interrupt for the
corresponding bit in the OUIR. When a bit is clear, the corresponding
bit in the OUIR will still be set on its event and cleared on read but will
not be passed on to the HIR.
7.6.37 Transmit RMON Interrupt Register
Name: TRIR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x1D0
Bits
Type
RO
Default Description
31:0
0x0000 RMON Tx Counter Rollover
0000
Set when the RMON Tx counter with the same index number as the bit
number has rolled over.
Note: All bits are cleared on read.
Rev. 1.2
71
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
