78Q8430 Data Sheet
DS_8430_001
Name: RCR
Reset Val: 0x0000_0002
Type Default Description
RW 10
Match Control
Block: CTL
Address: 0x1A8
Bits
1:0
How to generate a CAM reference word for the next pass. Match control
is described in detail in Table 27.
00 = DONE
10 = MD
01 = MX
11 = DROP
7.6.33 Que Status Interrupt Register
Name: QSIR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x1C0
Bits
Type
Default Description
QDR Rise
31
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Rising edge detected on QUE 7 QDR bit.
30
QDR Fall
Falling edge detected on QUE 7 QDR bit.
29
A Rise
Rising edge detected on QUE 7 QSR A bit. (See QSR)
28
B Rise
Rising edge detected on QUE 7 QSR B bit. (See QSR)
27:24
23:20
19:16
15:12
11:8
7:4
QUE 6
QDR Rise, QDR Fall, A Rise and B Rise interrupt bits for QUE 6.
QUE 5
QDR Rise, QDR Fall, A Rise and B Rise interrupt bits for QUE 5.
QUE 4
QDR Rise, QDR Fall, A Rise and B Rise interrupt bits for QUE 4.
QUE 3
QDR Rise, QDR Fall, A Rise and B Rise interrupt bits for QUE 3.
QUE 2
QDR Rise, QDR Fall, A Rise and B Rise interrupt bits for QUE 2.
QUE 1
QDR Rise, QDR Fall, A Rise and B Rise interrupt bits for QUE 1.
3:0
QUE 0
QDR Rise, QDR Fall, A Rise and B Rise interrupt bits for QUE 0.
Note: All bits are cleared on read.
7.6.34 Que Status Mask Register
Name: QSMR
Reset Val: 0x0000_0000
Default Description
QUE Status Interrupt Mask
Block: CTL
Address: 0x1C4
Bits
Type
RW
31:0
When a bit is set it enables the QUE status interrupt for the
corresponding bit in the QSIR. When a bit is clear, the corresponding
bit in the QSIR will still be set on its event and cleared on read but will
not be passed on to the HIR.
70
Rev. 1.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
