DS_8430_001
78Q8430 Data Sheet
7.6.31 Rule Match Register
Name: RMR
Reset Val: 0xFE3E_FF00
Block: CTL
Address: 0x1A4
Bits
Type
Default Description
31:25
RW
0x7F
0x1F
Previous Hit Mask
Mask bits to match for the previous hit match. A zero means the
corresponding bit in the previous hit match does not have to match to
be a hit.
24
X
Reserved
23:17
RW
Previous Hit Match
This CAM entry matches against the address of the previous CAM hit.
16
X
Reserved
15:8
RW
0xFF
0x00
Data Mask
Mask bits to match for the data match. A zero means the
corresponding bit in the data match does not have to match to be a hit.
7:0
RW
Data Match
This CAM field matches against either the packet byte or the control
logic ‘X’ register value selected by the match control field of the control
word register.
Note:
1. If all previous hit mask bits are zero, then the rule is disabled and will never match.
2. The RMR value is not valid for CAR ADDR values of zero or one.
7.6.32 Rule Control Register
Name: RCR
Reset Val: 0x0000_0002
Block: CTL
Address: 0x1A8
Bits
Type Default Description
31:22
21:16
X
Reserved
RW
0x00
Byte Offset
When this rule matches, do not attempt another match for this number of
bytes. A zero means that the very next byte will be executed. A value of
one means that the very next packet byte is ignored but the byte after
that is executed, etc. When this field is used to initialize the counter, no
offset is applied (see the TOC Control Logic Action).
15:8
7
X
Reserved
RW
0
Interrupt
When a match is made for this rule then trigger an interrupt to the host.
6:2
RW
0x0
Control Logic Action
Specifies what action to take when a match is made.
The Control Logic Actions are described in detail in Table 26.
0x0 = NOP
0x14 = THXA
0x2 = PAUSE 0x15 = SETMC
0x4 = WAKE 0x16 = VLAN
0x6 = IPCK
0x7 = TIPO
0x8 = TDX
0xA = TAX
0xC = TAXH
0xD = TAXL
0x10 = TXA
0x17 = SETBC
0x18 = TOC
0x1A = DEC
0x1B = MCTL
0x1C = TDPH
0x1D = TDLTH
0x1E = TDPL
0x12 = TLXA 0x1F = TDLTL
Rev. 1.2
69
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
