78Q8430 Data Sheet
DS_8430_001
Address: 0x198
Name: PMCAP
Reset Val: 0x120A_4801
Block: CTL
Bits
Type
Default Description
15:8
RO
0x48
Next
Reads back 0x48. Points to next capability.
7:0
RO
0x01
ID
Reads back 0x01.
7.6.29 Power Management Control and Status Register
Name: PMCSR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x19C
Bits
Type
Default Description
31:24
23:22
X
Reserved
RW
00
00
00
Psmarg1
Voltage regulator #1 margin.
21:20
19:18
RW
RW
Psmarg2
Voltage regulator #2 margin.
Psmarg3
Voltage regulator #3 margin.
17:16
15
X
Reserved
RW
0
PME
Power management event status. This bit is set by a WAKE signal from
the CAM and only cleared when the host writes a 1 to this bit.
14:9
8
X
Reserved
RW
0
PME_ENB
Enables assertion of PME when there is a power management event.
7:2
1:0
X
Reserved
RW
00
PS
Present power management state, 01b = D1, 00b = D0. (Any non-zero
value here tells the part that the host is in power down mode). In any
state other than D0, wake signals from classification are allowed to
generate PME interrupts and the movement of receive data into QUEs
is inhibited.
7.6.30 CAM Address Register
Name: CAR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x1A0
Bits
31:7
6:0
Type
X
Default Description
Reserved
RW
0x00
ADDR
CAM address of rule being accessed by the RMR and RCR.
68
Rev. 1.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
