DS_8430_001
78Q8430 Data Sheet
7.6.25 Host Not Responding Count Register
Name: HNRCR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x188
Bits
Type
RW
Default Description
Count
31:0
Number of system cycles to wait for the host to respond to a wake
condition before sending an HNR response.
7.6.26 Wake Up Status Register
Name: WUSR Reset Val: 0x0000_0000
Block: CTL
Address: 0x18C
Bits
31:8
7:0
Type
Default Description
Reserved
X
RO
Class
The classification result that triggered the wake up event.
7.6.27 Water Mark Values Register
Name: WMVR Reset Val: 0x0000_0400
Block: CTL
Address: 0x190
Bits
31
Type
Default Description
X
Reserved
30:24
RO
0x7D
0x00
0x04
0x00
Free
A count of the number of free memory blocks in the memory manager.
23
X
Reserved
22:16
RW
Interrupt
Minimum number of free blocks before the host is interrupted.
15
X
Reserved
14:8
RW
Headroom
Minimum number of free blocks before the MAC receiver is halted.
7
X
Reserved
6:0
RW
PAUSE
Minimum number of free blocks before the PAUSE packet is sent.
Note: For all watermarks, a value of zero will disable the related feature.
7.6.28 Power Management Capabilities
Name: PMCAP
Reset Val: 0x120A_4801
Block: CTL
Address: 0x198
Bits
Type
Default Description
31:27
RO
0x02
Support
Power management events supported. This field always reads back
00010b to indicate PME from D1 is supported.
26
RO
RO
RO
RO
0
1
D2 Support
Reads back 0 to indicate D2 is not supported.
25
D1 Support
Reads back 1 to indicate D1 is supported.
24:20
19
0x00
1
Init
Reads back 00000b to indicate no device specific initialization.
CLK
Reads back 1 to indicate the clock (BUSCLK) is needed for PME
operation.
18:16
RO
010
VER
Reads back 010b to indicate specification version 1.1 compliance.
Rev. 1.2
67
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
