78Q8430 Data Sheet
DS_8430_001
7.6.21 Counter Management Register
Name: CMR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x16C
Bits
31:3
2
Type
Default Description
Reserved
X
RW
Freeze
When this bit is set, the values of the counters are frozen until the bit is
cleared. Countable events that occur while this bit is set are stored in a
FIFO and processed after the bit is cleared such that no counts are lost.
If the FIFO fills before the Freeze bit is cleared then the bit is
automatically cleared and the counters updated.
1
0
W
W
Clear Receive
When a 1 is written to this bit then all receive counters are automatically
cleared.
Clear Transmit
When a 1 is written to this bit than all transmit counters are
automatically cleared.
7.6.22 Snoop Control Register
Name: SNCR Reset Val: 0x0000_0000
Block: CTL
Address: 0x170
Bits
31:7
6:0
Type
Default Description
X
Reserved
RW
0x00
BLOCK
Pointer to the BLOCK that is accessed directly via the SNOOP register
space.
7.6.23 Interrupt Delay Count Register
Name: IDCR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x180
Bits
Type
Default Description
31:24
23:0
X
Reserved
RW
IDC
How long to delay the data received interrupt, measured in byte times.
7.6.24 Pause Delay Count Register
Name: PDCR Reset Val: 0x0000_0000
Block: CTL
Address: 0x184
Bits
31:17
16
Type
Default Description
Reserved
X
WO
Start
Start local pause. Writing a one to this bit triggers a local pause
condition immediately.
15:0
RW
Pause
How long to halt transmit QUEs for a local pause condition, measured in
delay quanta of 512 Rx bit times.
66
Rev. 1.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
