DS_8430_001
78Q8430 Data Sheet
6
RW
1
FullDup
1 = Full Duplex
0 = Half Duplex
The default setting for the MAC is full duplex mode. This bit needs to
be updated each time there is a link status change in the PHY.
5
4
RW
RW
0
1
SQE
Enable SQE checking.
No Ex Diff
Disable checking for excessive deferrals.
3
2
1
X
X
0
0
0
Reserved
Reserved
RW
No Rx CRC
When this bit is set, the MAC receiver will strip the CRC bytes from the
end of received frames after the CRC check is complete.
0
RW
0
No CRC Chk
When this bit is set, CRC checking is disabled. This bit should never be
set when the No Rx CRC bit is set as there will be no way to verify the
CRC.
7.6.19 Count Data Register
Name: CDR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x164
Bits
Type
Default Description
Count
31:0
RW
Value of the counter indicated by CCR.
7.6.20 Counter Control Register
Name: CCR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x168
Bits
31:11
10
Type
X
Default Description
Reserved
RW
Auto Increment
When this bit is set, the address of the counter being accessed is
automatically incremented after each access to the CDR.
9
8
RW
RW
Clear on Read
When this bit is set, the counter being read is automatically cleared to
zero after each access to the CDR.
Access Mode
When this bit is clear, the CDR is in read mode. When set, the CDR is
in write mode.
7:6
5:0
X
Reserved
RW
Address
Address of the counter to access. (00 to 0E, Transmit Counters; 0F to
25, Receive Counters)
Rev. 1.2
65
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
