78Q8430 Data Sheet
DS_8430_001
7.6.17 PROM Control Register
Name: PRCR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x14C
Bits
31:9
8
Type
Default Description
X
0000
0
Reserved
RW
Busy
Writing a 1 initiates the EEPROM data transfer. The hardware will clear
the bit when the operation completes.
7:6
5:0
RW
RW
0x0
Operation
1 1 = Erase.
1 0 = Read.
0 1 = Write.
0 0 = Enable or Disable Writing, as specified in PROM Addr:
[5:4] = 11, Enable
[5:4] = 00, Disable
0x00
PROM Addr
Address of the EEPROM to access.
7.6.18 MAC Control Register
Name: MCR Reset Val: 0x0080_0050
Default Description
Block: CTL
Address: 0x154
Bits
31:28
27
Type
X
0000
0
Reserved
RW
Tx Enable
When this bit is clear transmitting stops immediately.
26
25
24
23
RW
RW
RW
RW
0
0
0
1
Tx Halt
When this bit is set transmitting stops at the end of the current frame.
Rx Enable
When this bit is clear receiving stops immediately.
Rx Halt
When this bit is set receiving stops at the end of the current frame.
Rx Drop Error
When this bit is set then an error in the first 256 bytes will cause a
packet to be dropped. If clear, error packets are forwarded to the host.
22
21
RW
RW
0
0
Keep Dropped Status
Normally, the status for a dropped frame is not added to the receive
status FIFO. When this bit is set then a status for all frames, including
dropped frames, is added to the receive status FIFO. The status for a
dropped frame will have a size of zero in the RPSR.
Jumbo OK
Normally frames in excess of the maximum allowed by 802.3 are
flagged as bad. If this bit is set then larger frame sizes are allowed.
20:18
17
0000
0
Reserved
RW
RW
MACRST
Software re-initialization. Setting this bit will also automatically set both
Rx and Tx Halt bits and clear both Rx and Tx Enable bits. This bit is
only cleared by writing a zero.
16
0
MACLOOP
Loopback mode for the MAC.
15:8
7
X
0x000
0
Reserved
RW
No Rx PAD
Strip the padding bytes from the end of received frames that are 64
bytes in length. When the padding is stripped from a frame the CRC is
stripped as well.
64
Rev. 1.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
