DS_8430_001
78Q8430 Data Sheet
7.6.13 BIST Bypass Mode Data Register
Name: BBDR
Reset Val: N/A
Block: CTL
Address: 0x13C
Bits
Type
R/W
Default Description
RAM Data
31:0
Reads and writes to these bits go directly to the QMEM RAM at the
location indicated by BCR only when the BIST mode is set to BYPASS.
7.6.14 Station Management Data Register
Name: MDDAR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x140
Bits
Type
Default Description
31:16
X
0000
Reserved
15:0
RW
0
SMI Data
Data read from or data to be written to the PHY. See Section 7.7.
7.6.15 Station Management Control and Address Register
Name: MDCAR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x144
Bits
31:13
12
Type
Default Description
X
0000
0
Reserved
RW
Preamble
Writing a 1 suppresses the generation of the 32-bit PHY station
management preamble before the PHY register transfer. The internal
PHY of the 8430 does not require the preamble.
11
10
RW
RW
0
0
Busy
Writing a 1 initiates the PHY register transfer. The hardware will clear
the bit when the operation completes.
RegWr
Writing a 1 indicated the MDDAR data is to be written to the PHY.
Writing a 0 causes the PHY register to be read and the data placed in
the MDDAR .
9:5
4:0
RW
RW
0
0
PHY Addr
Address of the PHY to access.
PHY Reg
Address of the PHY register to access.
7.6.16 PROM Data Register
Name: PRDR Reset Val: 0x0000_0000
Default Description
Block: CTL
Address: 0x148
Bits
Type
31:16
15:0
X
0000
0000
Reserved
RW
PROM Data
Data to write to or read from the EEPROM device.
Rev. 1.2
63
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
