78Q8430 Data Sheet
DS_8430_001
7.6.11 Receive Data Status Register
Name: RDSR
Reset Val: 0x0001_0000
Block: CTL
Address: 0x134
Bits
31:25
24
Type
Default Description
Reserved
R
0
EOF
When set this bit indicates that the next data word read from QUE0 will
be the end of its frame.
23:17
16
Reserved
R
R
1
QUE0 Empty
When set this bit indicates that QUE0 contains no data.
15:2
1:0
Reserved
00b
QUE0 Data Size
The number of valid bytes in the next data word read from QUE0.
7.6.12 BIST Control Register
Name: BCR Reset Val: 0x2010_0000
Block: CTL
Address: 0x138
Bits
Type
Default Description
BIST Start
31
W
Writing a 1 to this bit triggers the selected BIST test (see BIST Mode
below).
30
29
R
R
0
1
Fail
The BIST operation failed.
Pass
The BIST operation passed.
28:21
20
Reserved
R/W
1
Auto Increment
When set, the RAM Address field will auto-increment after each RAM
access.
19
R/W
R/W
BIST Enable
Enable BIST mode operation.
18:16
000
BIST Mode
Set the BIST test mode:
000b – Reserved.
001b – PATTERN.
010b – FILL 0.
011b – READ 0.
100b – FILL 1.
101b – READ 1.
110b – BYPASS.
111b – Reserved.
Reserved
15:14
13:0
R/W
0x000
RAM Address
Set the address of the RAM that is accessed via BBDR in BYPASS
mode.
62
Rev. 1.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
