ICM-20602
9.24 REGISTER 35 – FIFO ENABLE
Register Name: FIFO_EN
Register Type: READ/WRITE
Register Address: 35 (Decimal); 23 (Hex)
BIT
[7:5]
NAME
-
FUNCTION
Reserved
1 – write TEMP_OUT_H, TEMP_OUT_L, GYRO_XOUT_H, GYRO_XOUT_L, GYRO_YOUT_H,
GYRO_YOUT_L, GYRO_ZOUT_H, and GYRO_ZOUT_L to the FIFO at the sample rate; If
enabled, buffering of data occurs even if data path is in standby.
0 – function is disabled
[4]
GYRO_FIFO_EN
1 – write ACCEL_XOUT_H, ACCEL_XOUT_L, ACCEL_YOUT_H, ACCEL_YOUT_L,
ACCEL_ZOUT_H, ACCEL_ZOUT_L, TEMP_OUT_H, and TEMP_OUT_L to the FIFO at the
sample rate;
0 – function is disabled
Reserved
[3]
ACCEL_FIFO_EN
-
[2:0]
NOTE: If both GYRO_FIFO_EN And ACCEL_FIFO_EN are 1, write ACCEL_XOUT_H, ACCEL_XOUT_L, ACCEL_YOUT_H, ACCEL_YOUT_L, ACCEL_ZOUT_H, ACCEL_ZOUT_L,
TEMP_OUT_H, TEMP_OUT_L, GYRO_XOUT_H, GYRO_XOUT_L, GYRO_YOUT_H, GYRO_YOUT_L, GYRO_ZOUT_H, and GYRO_ZOUT_L to the FIFO at the sample rate.
9.25 REGISTER 54 – FSYNC INTERRUPT STATUS
Register Name: FSYNC_INT
Register Type: READ to CLEAR
Register Address: 54 (Decimal); 36 (Hex)
BIT
NAME
FUNCTION
This bit automatically sets to 1 when a FSYNC interrupt has been generated. The bit clears
to 0 after the register has been read.
[7]
FSYNC_INT
9.26 REGISTER 55 – INT/DRDY PIN / BYPASS ENABLE CONFIGURATION
Register Name: INT_PIN_CFG
Register Type: READ/WRITE
Register Address: 55 (Decimal); 37 (Hex)
BIT
NAME
FUNCTION
1 – The logic level for INT/DRDY pin is active low.
0 – The logic level for INT/DRDY pin is active high.
1 – INT/DRDY pin is configured as open drain.
[7]
INT_LEVEL
[6]
[5]
[4]
[3]
INT_OPEN
0 – INT/DRDY pin is configured as push-pull.
1 – INT/DRDY pin level held until interrupt status is cleared.
0 – INT/D‘DY piꢁ iꢁdiꢃates iꢁteꢂꢂupt pulseꢋs ꢊidth is ꢇꢆus.
1 – Interrupt status is cleared if any read operation is performed.
0 – Interrupt status is cleared only by reading INT_STATUS register
1 – The logic level for the FSYNC pin as an interrupt is active low.
0 – The logic level for the FSYNC pin as an interrupt is active high.
When this bit is equal to 1, the FSYNC pin will trigger an interrupt when it transitions to the
level specified by FSYNC_INT_LEVEL. When this bit is equal to 0, the FSYNC pin is disabled
from causing an interrupt.
LATCH_INT_EN
INT_RD_CLEAR
FSYNC_INT_LEVEL
[2]
FSYNC_INT_MODE_EN
-
[1:0]
Reserved.
Document Number: DS-000176
Revision: 1.0
Page 41 of 57
Revision Date: 10/03/2016
TDK [ TDK ELECTRONICS ]
