ICM-20602
9.19 REGISTER 29 – ACCELEROMETER CONFIGURATION 2
Register Name: ACCEL_CONFIG2
Register Type: READ/WRITE
Register Address: 29 (Decimal); 1D (Hex)
BIT
NAME
FUNCTION
Averaging filter settings for Low Power Accelerometer mode:
0 = Average 4 samples
1 = Average 8 samples
[5:4]
DEC2_CFG[1:0]
2 = Average 16 samples
3 = Average 32 samples
[3]
[2:0]
ACCEL_FCHOICE_B
A_DLPF_CFG
Used to bypass DLPF as shown in the table below.
Accelerometer low pass filter setting as shown in table 2 below.
Accelerometer Data Rates and Bandwidths (Low-Noise Mode)
Accelerometer
ACCEL_FCHOICE_B
A_DLPF_CFG
3-dB BW
(Hz)
Noise BW
(Hz)
Rate
(kHz)
1
0
0
0
0
0
0
0
0
X
0
1
2
3
4
5
6
7
1046.0
218.1
218.1
99.0
1100.0
235.0
235.0
121.3
61.5
4
1
1
1
1
1
1
1
1
44.8
21.2
31.0
10.2
15.5
5.1
7.8
420.0
441.6
The data output rate of the DLPF filter block can be further reduced by a factor of 1/(1+SMPLRT_DIV), where SMPLRT_DIV is an 8-bit
integer. Following is a small subset of ODRs that are configurable for the accelerometer in the low-noise mode in this manner (Hz):
3.91, 7.81, 15.63, 31.25, 62.50, 125, 250, 500, 1K
The following table lists the approximate accelerometer filter bandwidths available in the low-power mode of operation for some
example ODRs.
In the low-power mode of operation, the accelerometer is duty-cycled. The following table shows some example configurations for
accelerometer low power mode.
Document Number: DS-000176
Revision: 1.0
Page 38 of 57
Revision Date: 10/03/2016
TDK [ TDK ELECTRONICS ]
