ICM-20602
9.33 REGISTER 96 TO 97 – FIFO WATERMARK THRESHOLD IN NUMBER OF BYTES
Register Name: FIFO_WM_TH1
Register Type: READ/WRITE
Register Address: 96 (Decimal); 60 (Hex)
BIT
NAME
FUNCTION
FIFO watermark threshold in number of bytes. Watermark interrupt is
disaꢎled if the thꢂeshold is set to ꢏꢆꢐ. Default ꢄalue is ꢆꢆꢆꢆꢆꢆꢆꢆ.
[1:0]
FIFO_WM_TH[9:8]
Register Name: FIFO_WM_TH2
Register Type: READ/WRITE
Register Address: 97 (Decimal); 61 (Hex)
BIT
NAME
FUNCTION
FIFO watermark threshold in number of bytes. Watermark interrupt is
disaꢎled if the thꢂeshold is set to ꢏꢆꢐ. Default ꢄalue is ꢆꢆꢆꢆꢆꢆꢆꢆ.
[7:0]
FIFO_WM_TH[7:0]
The register FIFO_WM_TH[9:0] sets the FIFO watermark threshold level (0 - 1023). User should ensure that bit 7 of register 0x1A is
set to 0 before using this feature. When the FIFO count is at or above the watermark level (FIFO_COUNT[15:0] ≥ FIFO_WM_TH[9:0])
and the system is not in the middle of a FIFO read, an interrupt is triggered. The interrupt will set the FIFO watermark interrupt
status register field FIFO_WM_INT = 1, and the INT pin will issue a pulse if configured in pulse mode, or set to the active level if
configured in latch mode. Register bit FIFO_WM_INT is not read-to-clear, unlike the other interrupts. Rather, whenever FIFO_R_W
register is read, FIFO_WM_INT status bit is cleared automatically. At the same time, the INT pin will be cleared as well if it is
configured in latch mode.
The FIFO watermark interrupt and the INT pin are cleared upon the first read (and only the first read) of the FIFO. If, at the end of
the FIFO read, the FIFO count is at or above the watermark level, the interrupt status bit and INT pin will again be set. If the INT pin is
configured for latched operation, it will wait until the host completes the read to set to the active level.
9.34 REGISTER 104 – SIGNAL PATH RESET
Register Name: SIGNAL_PATH_RESET
Register Type: READ/WRITE
Register Address: 104 (Decimal); 68 (Hex)
BIT
[7:2]
NAME
-
FUNCTION
Reserved
Reset accel digital signal path. NOTE: Sensor registers are not cleared. Use SIG_COND_RST to
clear sensor registers.
[1]
[0]
ACCEL_RST
TEMP_RST
Reset temp digital signal path. NOTE: Sensor registers are not cleared. Use SIG_COND_RST to
clear sensor registers.
9.35 REGISTER 105 – ACCELEROMETER INTELLIGENCE CONTROL
Register Name: ACCEL_INTEL_CTRL
Register Type: READ/WRITE
Register Address: 105 (Decimal); 69 (Hex)
BIT
[7]
NAME
FUNCTION
ACCEL_INTEL_EN
This bit enables the Wake-on-Motion detection logic
0 – Do not use
[6]
ACCEL_INTEL_MODE
1 – Compare the current sample with the previous sample
Reserved
[5:2]
[1]
-
To avoid limiting sensor output to less than 0x7FFF, set this bit to 1. This should be done
every time the ICM-20602 is powered up.
OUTPUT_LIMIT
0 – Set WoM interrupt on the OR of all enabled accelerometer thresholds
1 – Set WoM interrupt on the AND of all enabled accelerometer threshold
Default setting is 0
[0]
WOM_TH_MODE
Document Number: DS-000176
Revision: 1.0
Page 45 of 57
Revision Date: 10/03/2016
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