UPSD3212C, UPSD3212CV
Port D – Functionality and Structure
Port D has two I/O pins (only one pin, PD1, in the
52-pin package). See Figure 57 and Figure 58.
This port does not support Address Out Mode, and
therefore no Control Register is required. Of the
eight bits in the Port D registers, only Bits 2 and 1
are used to configure pins PD2 and PD1.
■ CPLD Input – direct input to the CPLD, no Input
Macrocells (IMC)
■ Slew rate – pins can be set up for fast slew rate
Port D pins can be configured in PSDsoft Express
as input pins for other dedicated functions:
Port D can be configured to perform one or more
of the following functions:
■ CLKIN (PD1) as input to the macrocells flip-
flops and APD counter
■ MCU I/O Mode
■ PSD Chip Select Input (CSI, PD2). Driving this
signal High disables the Flash memory, SRAM
and CSIOP.
■ CPLD Output – External Chip Select (ECS1-
ECS2)
Figure 57. Port D Structure
DATA OUT
REG.
DATA OUT
D
Q
WR
PORT D PIN
OUTPUT
MUX
[
]
ECS 2:1
READ MUX
OUTPUT
SELECT
P
D
B
DATA IN
ENABLE PRODUCT
TERM (.OE)
DIR REG.
D
Q
WR
CPLD-INPUT
AI06606
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STMICROELECTRONICS [ ST ]
