UPSD3212C, UPSD3212CV
Ports A and B – Functionality and Structure
Ports A and B have similar functionality and struc-
ture, as shown in Figure 55. The two ports can be
configured to perform one or more of the following
functions:
■ CPLD Input – Via the Input Macrocells (IMC).
■ Latched Address output – Provide latched
address output as per Table 71.
■ Open Drain/Slew Rate – pins PA3-PA0 and
PB3-PB0 can be configured to fast slew rate,
pins PA7-PA4 and PB7-PB4 can be configured
to Open Drain Mode.
■ MCU I/O Mode
■ CPLD Output – Macrocells McellAB7-McellAB0
can be connected to Port A or Port B. McellBC7-
McellBC0 can be connected to Port B or Port C.
■ Peripheral Mode – Port A only (80-pin package)
Figure 55. Port A and Port B Structure
DATA OUT
REG.
DATA OUT
D
Q
WR
PORT
A OR B PIN
ADDRESS
ALE
ADDRESS
D
G
Q
[
]
A 7:0
OUTPUT
MUX
MACROCELL OUTPUTS
READ MUX
P
D
B
OUTPUT
SELECT
DATA IN
CONTROL REG.
ENABLE OUT
D
Q
WR
WR
DIR REG.
D
Q
(
)
ENABLE PRODUCT TERM .OE
CPLD-INPUT
INPUT
MACROCELL
AI06605
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STMICROELECTRONICS [ ST ]
