UPSD3212C, UPSD3212CV
Figure 54. Peripheral I/O Mode
RD
PSEL0
PSEL
PSEL1
D0-D7
VM REGISTER BIT 7
PA0-PA7
DATA BUS
WR
AI02886
Table 69. Port Operating Modes
(2)
Port Mode
MCU I/O
Port B
Port C
Port D
Port A
Yes
Yes
Yes
No
Yes
PLD I/O
McellAB Outputs
McellBC Outputs
Additional Ext. CS Outputs No
PLD Inputs
Address Out
Peripheral I/O
JTAG ISP
Yes
No
Yes
Yes
No
No
No
Yes
Yes
(3)
Yes
No
Yes
Yes
Yes
Yes (A7 – 0)
Yes (A7 – 0)
No
No
No
No
No
Yes
No
No
No
(1)
Yes
Note: 1. JTAG pins (TMS, TCK, TDI, TDO) are dedicated pins.
2. Port A is not available in the 52-pin package.
3. On pins PC2, PC3, PC4 and PC7 only.
Table 70. Port Operating Mode Settings
Control Register
Setting
Direction Register
Setting
Mode
MCU I/O
Defined in PSDsoft
VM Register Setting
1 = output,
0 = input (Note 1)
Declare pins only
Logic equations
Declare pins only
0
N/A
N/A
N/A
PLD I/O
N/A
1
(Note 1)
Address Out
(Port A,B)
1 (Note 1)
Peripheral I/O
(Port A)
Logic equations
(PSEL0 & 1)
N/A
N/A
PIO Bit = 1
Note: N/A = Not Applicable
1. The direction of the Port A,B,C, and D pins are controlled by the Direction Register ORed with the individual output enable product
term (.oe) from the CPLD AND Array.
Table 71. I/O Port Latched Address Output Assignments
Port A (PA3-PA0)
Address a3-a0
Port A (PA7-PA4)
Address a7-a4
Port B (PB3-PB0)
Address a3-a0
Port B (PB7-PB4)
Address a7-a4
106/152
STMICROELECTRONICS [ ST ]
