UPSD3212C, UPSD3212CV
I/O PORTS (PSD MODULE)
There are four programmable I/O ports: Ports A, B,
C, and D in the PSD MODULE. Each of the ports
is eight bits except Port D, which is 3 bits. Each
port pin is individually user configurable, thus al-
lowing multiple functions per port. The ports are
configured using PSDsoft Express Configuration
or by the MCU writing to on-chip registers in the
CSIOP space. Port A is not available in the 52-pin
package.
that pin is no longer available for other purposes.
Exceptions are noted.
As shown in Figure 53, the ports contain an output
multiplexer whose select signals are driven by the
configuration bits in the Control Registers (Ports A
and B only) and PSDsoft Express Configuration.
Inputs to the multiplexer include the following:
■ Output data from the Data Out register
■ Latched address outputs
The topics discussed in this section are:
■ CPLD macrocell output
■ General Port architecture
■ External Chip Select (ECS1-ECS2) from the
■ Port operating modes
CPLD.
■ Port Configuration Registers (PCR)
■ Port Data Registers
The Port Data Buffer (PDB) is a tri-state buffer that
allows only one source at a time to be read. The
Port Data Buffer (PDB) is connected to the Internal
Data Bus for feedback and can be read by the
MCU. The Data Out and macrocell outputs, Direc-
tion and Control Registers, and port pin input are
all connected to the Port Data Buffer (PDB).
■ Individual Port functionality.
General Port Architecture
The general architecture of the I/O Port block is
shown in Figure 53. Individual Port architectures
are shown in Figure 55 to Figure 58. In general,
once the purpose for a port pin has been defined,
Figure 53. General I/O Port Architecture
DATA OUT
REG.
DATA OUT
D
Q
WR
ADDRESS
ALE
ADDRESS
PORT PIN
D
G
Q
OUTPUT
MUX
MACROCELL OUTPUTS
EXT CS
READ MUX
P
D
B
OUTPUT
SELECT
DATA IN
CONTROL REG.
ENABLE OUT
D
Q
WR
WR
DIR REG.
D
Q
(
)
ENABLE PRODUCT TERM .OE
INPUT
MACROCELL
CPLD-INPUT
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STMICROELECTRONICS [ ST ]
