Electrical characteristics
STM32F405xx, STM32F407xx
(1)(2)
Table 78. Asynchronous multiplexed PSRAM/NOR write timings
th(NE_NWE)
tv(A_NE)
tv(NADV_NE)
tw(NADV)
FSMC_NWE high to FSMC_NE high hold time
FSMC_NEx low to FSMC_A valid
FSMC_NEx low to FSMC_NADV low
FSMC_NADV low time
THCLK
-
ns
ns
ns
ns
-
1
0
2
THCLK– 2
THCLK+ 1
FSMC_AD(address) valid hold time after
FSMC_NADV high)
th(AD_NADV)
THCLK–2
-
ns
th(A_NWE)
th(BL_NWE)
tv(BL_NE)
Address hold time after FSMC_NWE high
FSMC_BL hold time after FSMC_NWE high
FSMC_NEx low to FSMC_BL valid
THCLK
-
ns
ns
ns
ns
ns
THCLK–2
-
-
1.5
tv(Data_NADV) FSMC_NADV high to Data valid
-
THCLK–0.5
-
th(Data_NWE) Data hold time after FSMC_NWE high
THCLK
1. CL = 30 pF.
2. Based on characterization, not tested in production.
Synchronous waveforms and timings
Figure 59 through Figure 62 represent synchronous waveforms and Table 80 through
Table 82 provide the corresponding timings. The results shown in these tables are obtained
with the following FSMC configuration:
•
•
•
•
•
BurstAccessMode = FSMC_BurstAccessMode_Enable;
MemoryType = FSMC_MemoryType_CRAM;
WriteBurst = FSMC_WriteBurst_Enable;
CLKDivision = 1; (0 is not supported, see the STM32F40xxx/41xxx reference manual)
DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
In all timing tables, the THCLK is the HCLK clock period (with maximum
FSMC_CLK = 60 MHz).
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