STM32F405xx, STM32F407xx
Electrical characteristics
(1)(2)
Table 75. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings
tv(BL_NE)
th(BL_NOE)
FSMC_NEx low to FSMC_BL valid
FSMC_BL hold time after FSMC_NOE high
Data to FSMC_NEx high setup time
Data to FSMC_NOEx high setup time
Data hold time after FSMC_NOE high
Data hold time after FSMC_NEx high
FSMC_NEx low to FSMC_NADV low
FSMC_NADV low time
-
1.5
ns
ns
ns
ns
ns
ns
ns
ns
0
-
tsu(Data_NE)
tsu(Data_NOE)
th(Data_NOE)
th(Data_NE)
THCLK+4
-
THCLK+4
-
0
0
-
-
-
2
tv(NADV_NE)
tw(NADV)
-
THCLK
1. CL = 30 pF.
2. Based on characterization, not tested in production.
Figure 56. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
t
w(NE)
FSMC_NEx
FSMC_NOE
FSMC_NWE
t
t
t
h(NE_NWE)
v(NWE_NE)
w(NWE)
t
tv(A_NE)
h(A_NWE)
FSMC_A[25:0]
Address
tv(BL_NE)
t
h(BL_NWE)
FSMC_NBL[1:0]
NBL
t
t
v(Data_NE)
h(Data_NWE)
Data
FSMC_D[15:0]
FSMC_NADV(1)
t
v(NADV_NE)
t
w(NADV)
ai14990
1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.
(1)(2)
Table 76. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings
Symbol
Parameter
FSMC_NE low time
Min
Max
Unit
tw(NE)
tv(NWE_NE)
tw(NWE)
3THCLK
3THCLK+ 4 ns
FSMC_NEx low to FSMC_NWE low
FSMC_NWE low time
THCLK–0.5 THCLK+0.5 ns
THCLK–1
THCLK–1
-
THCLK+2
ns
ns
ns
th(NE_NWE)
tv(A_NE)
FSMC_NWE high to FSMC_NE high hold time
FSMC_NEx low to FSMC_A valid
-
0
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