Electrical characteristics
STM32F405xx, STM32F407xx
(1)(2)
Table 81. Synchronous non-multiplexed NOR/PSRAM read timings
(continued)
td(CLKL-NExH)
FSMC_CLK low to FSMC_NEx high (x= 0…2)
0
-
-
2
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low
td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high
3
td(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x=16…25)
FSMC_CLK low to FSMC_Ax invalid (x=16…25)
FSMC_CLK low to FSMC_NOE low
-
2
0
-
td(CLKL-AIV)
td(CLKL-NOEL)
td(CLKL-NOEH)
tsu(DV-CLKH)
th(CLKH-DV)
-
0.5
-
FSMC_CLK low to FSMC_NOE high
1.5
6
FSMC_D[15:0] valid data before FSMC_CLK high
FSMC_D[15:0] valid data after FSMC_CLK high
-
3
-
tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high
th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high
4
-
0
-
1. CL = 30 pF.
2. Based on characterization, not tested in production.
Figure 62. Synchronous non-multiplexed PSRAM write timings
BUSTURN = 0
t
t
w(CLK)
w(CLK)
FSMC_CLK
t
t
d(CLKL-NExL)
FSMC_NEx
d(CLKL-NExH)
Data latency = 0
d(CLKL-NADVH)
t
t
d(CLKL-NADVL)
FSMC_NADV
FSMC_A[25:0]
FSMC_NWE
t
t
t
d(CLKL-AIV)
d(CLKL-AV)
t
d(CLKL-NWEL)
d(CLKL-NWEH)
t
t
d(CLKL-Data)
d(CLKL-Data)
FSMC_D[15:0]
D1
D2
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
FSMC_NBL
t
t
d(CLKL-NBLH)
su(NWAITV-CLKH)
t
h(CLKH-NWAITV)
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DocID022152 Rev 4
STMICROELECTRONICS [ ST ]
