STM32F405xx, STM32F407xx
Electrical characteristics
Figure 59. Synchronous multiplexed NOR/PSRAM read timings
BUSTURN = 0
t
t
w(CLK)
w(CLK)
FSMC_CLK
Data latency = 0
d(CLKL-NExL)
t
t
t
d(CLKL-NExH)
FSMC_NEx
t
t
d(CLKL-NADVL)
d(CLKL-NADVH)
FSMC_NADV
t
d(CLKL-AIV)
d(CLKL-AV)
FSMC_A[25:16]
t
t
d(CLKL-NOEH)
d(CLKL-NOEL)
FSMC_NOE
t
t
t
h(CLKH-ADV)
d(CLKL-ADIV)
t
t
t
su(ADV-CLKH)
su(ADV-CLKH)
d(CLKL-ADV)
h(CLKH-ADV)
FSMC_AD[15:0]
AD[15:0]
t
D1
D2
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
FSMC_NWAIT
(WAITCFG = 1b, WAITPOL + 0b)
t
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
t
t
h(CLKH-NWAITV)
su(NWAITV-CLKH)
ai14893g
(1)(2)
Max
Table 79. Synchronous multiplexed NOR/PSRAM read timings
Symbol
Parameter
Min
Unit
tw(CLK)
FSMC_CLK period
2THCLK
-
0
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2)
td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2)
td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low
td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high
-
2
-
2
-
2
-
td(CLKL-AV)
td(CLKL-AIV)
FSMC_CLK low to FSMC_Ax valid (x=16…25)
FSMC_CLK low to FSMC_Ax invalid (x=16…25)
0
-
0
-
td(CLKL-NOEL) FSMC_CLK low to FSMC_NOE low
td(CLKL-NOEH) FSMC_CLK low to FSMC_NOE high
0
-
2
-
td(CLKL-ADV)
FSMC_CLK low to FSMC_AD[15:0] valid
4.5
-
td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid
0
6
tsu(ADV-CLKH) FSMC_A/D[15:0] valid data before FSMC_CLK high
-
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STMICROELECTRONICS [ ST ]
