Electrical characteristics
STM32F405xx, STM32F407xx
(1)(2)
Table 79. Synchronous multiplexed NOR/PSRAM read timings
(continued)
ns
th(CLKH-ADV) FSMC_A/D[15:0] valid data after FSMC_CLK high
0
4
0
-
tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high
th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high
-
ns
ns
-
1. CL = 30 pF.
2. Based on characterization, not tested in production.
Figure 60. Synchronous multiplexed PSRAM write timings
BUSTURN = 0
t
t
w(CLK)
w(CLK)
FSMC_CLK
Data latency = 0
d(CLKL-NExL)
t
t
d(CLKL-NExH)
FSMC_NEx
t
t
d(CLKL-NADVL)
d(CLKL-NADVH)
FSMC_NADV
t
t
t
d(CLKL-AIV)
d(CLKL-AV)
FSMC_A[25:16]
FSMC_NWE
t
d(CLKL-NWEL)
d(CLKL-NWEH)
t
t
d(CLKL-ADIV)
t
d(CLKL-Data)
D1
t
d(CLKL-Data)
d(CLKL-ADV)
FSMC_AD[15:0]
AD[15:0]
D2
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
FSMC_NBL
t
t
h(CLKH-NWAITV)
su(NWAITV-CLKH)
t
d(CLKL-NBLH)
ai14992g
(1)(2)
Table 80. Synchronous multiplexed PSRAM write timings
Symbol
Parameter
Min
Max
Unit
tw(CLK)
FSMC_CLK period
2THCLK
-
1
-
ns
ns
ns
ns
ns
ns
td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2)
td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2)
td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low
td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high
-
1
-
0
-
0
-
td(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x=16…25)
0
144/185
DocID022152 Rev 4
STMICROELECTRONICS [ ST ]
