STM32F405xx, STM32F407xx
Electrical characteristics
(1)(2)
Table 80. Synchronous multiplexed PSRAM write timings
td(CLKL-AIV)
FSMC_CLK low to FSMC_Ax invalid (x=16…25)
8
-
-
ns
ns
ns
ns
ns
ns
ns
ns
td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low
td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high
td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid
td(CLKL-DATA) FSMC_A/D[15:0] valid data after FSMC_CLK low
td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high
0.5
0
0
-
-
-
3
-
0
4
0
tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high
th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high
-
-
1. CL = 30 pF.
2. Based on characterization, not tested in production.
Figure 61. Synchronous non-multiplexed NOR/PSRAM read timings
BUSTURN = 0
t
t
w(CLK)
w(CLK)
FSMC_CLK
t
t
d(CLKL-NExH)
d(CLKL-NExL)
Data latency = 0
d(CLKL-NADVH)
FSMC_NEx
t
t
d(CLKL-NADVL)
FSMC_NADV
t
t
d(CLKL-AIV)
d(CLKL-AV)
FSMC_A[25:0]
t
t
d(CLKL-NOEL)
d(CLKL-NOEH)
FSMC_NOE
t
t
su(DV-CLKH)
h(CLKH-DV)
su(DV-CLKH)
t
t
h(CLKH-DV)
FSMC_D[15:0]
FSMC_NWAIT
D1
D2
h(CLKH-NWAITV)
t
t
su(NWAITV-CLKH)
(WAITCFG = 1b, WAITPOL + 0b)
t
t
h(CLKH-NWAITV)
su(NWAITV-CLKH)
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
t
t
su(NWAITV-CLKH)
h(CLKH-NWAITV)
ai14894f
(1)(2)
Table 81. Synchronous non-multiplexed NOR/PSRAM read timings
Symbol
tw(CLK)
td(CLKL-NExL)
Parameter
Min
Max
Unit
FSMC_CLK period
2THCLK –0.5
-
-
ns
ns
FSMC_CLK low to FSMC_NEx low (x=0..2)
0.5
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STMICROELECTRONICS [ ST ]
