CONTROLLER AREA NETWORK (bxCAN)
CONTROLLER AREA NETWORK (Cont’d)
10.10.8.2 Mailbox Registers
Bit 3 = TXOK Transmission OK
- Read/Clear
The hardware updates this bit after each transmis-
sion attempt.
This chapter describes the registers of the transmit
and receive mailboxes. Refer to Section 10.10.5.5
Message Storage for detailed register mapping.
0: The previous transmission failed
1: The previous transmission was successful
Transmit and receive mailboxes have the same
registers except:
Note: This bit has the same value as the corre-
sponding TXOKx bit in the CTSR register.
– MCSR register in a transmit mailbox is replaced
by MFMI register in a receive mailbox.
– A receive mailbox is always write protected.
Bit 2 = RQCP Request Completed
- Read/Clear
Set by hardware when the last request (transmit or
abort) has been performed.
– A transmit mailbox is write enable only while
empty, corresponding TME bit in the CTPR reg-
ister set.
Cleared by software writing a “1” or by hardware
on transmission request.
MAILBOX CONTROL STATUS REGISTER
(MCSR)
Note: This bit has the same value as the corre-
sponding RQCPx bit of the CTSR register.
Read / Write
Reset Value: 0000 0000 (00h)
Clearing this bit clears all the status bits (TX-
OK, ALST and TERR) in the MCSR register and
the RQCP and TXOK bits in the CTSR register.
7
0
0
0
TERR ALST TXOK RQCP ABRQ TXRQ
Bit 1 = ABRQ Abort Request for Mailbox
- Read/Set
Set by software to abort the transmission request
for the corresponding mailbox.
Bit 7:6 = Reserved. Forced to 0 by hardware.
Cleared by hardware when the mailbox becomes
empty.
Bit 5 = TERR Transmission Error
- Read/Clear
This bit is updated by hardware after each trans-
mission attempt.
Setting this bit has no effect when the mailbox is
not pending for transmission.
0: The previous transmission was successful
1: The previous transmission failed due to an error
Bit 0 = TXRQ Transmit Mailbox Request
- Read/Set
Set by software to request the transmission for the
corresponding mailbox.
Bit 4 = ALST Arbitration Lost
- Read/Clear
This bit is updated by hardware after each trans-
mission attempt.
Cleared by hardware when the mailbox becomes
empty.
0: The previous transmission was successful
1: The previous transmission failed due to an arbi-
tration lost
Note: This register is implemented only in transmit
mailboxes. In receive mailboxes, the MFMI regis-
ter is mapped at this location.
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