CONTROLLER AREA NETWORK (bxCAN)
CONTROLLER AREA NETWORK (Cont’d)
CAN BIT TIMING REGISTER 0 (CBTR0)
CAN FILTER PAGE SELECT REGISTER
(CFPSR)
This register can only be accessed by the software
when the CAN hardware is in configuration mode.
Read / Write
All bits of this register are set and cleared by soft-
ware.
Read / Write
Reset Value: 0000 0000 (00h)
Reset Value: 0000 0000 (00h)
7
0
7
0
0
SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0
0
0
0
0
FPS2 FPS1 FPS0
Bit 7:6 SJW[1:0] Resynchronization Jump Width
These bits define the maximum number of time
quanta the CAN hardware is allowed to lengthen
or shorten a bit to perform the resynchronization.
Bit 7:3 = Reserved. Forced to 0 by hardware.
Bit 2:0 = FPS[2:0] Filter Page Select
- Read/Write
This register contains the filter page number avail-
able in page 54.
Bit 5:0 BRP[5:0] Baud Rate Prescaler
These bits define the length of a time quantum.
tq = (BRP+1)/fsys
Table 64. Filter Page Selection
For more information on bit timing, please refer to
Section 10.10.5.7 Bit Timing.
FPS[2:0]
Filter Page Selected in Page 54
Acceptance Filter 0:1
Acceptance Filter 2:3
Acceptance Filter 4:5
Acceptance Filter 6:7
Filter Configuration
0
1
2
3
4
5
6
7
CAN BIT TIMING REGISTER 1 (CBTR1)
Read / Write
Reset Value: 0001 0011 (23h)
7
0
0
Filter Configuration
TS22 TS21 TS20 TS13 TS12 TS11 TS10
Filter Configuration
Filter Configuration
Bit 7 = Reserved. Forced to 0 by hardware.
Bit 6:4 TS2[2:0] Time Segment 2
These bits define the number of time quanta in
Time Segment 2.
t
= t
x (TS2[2:0] + 1),
BS2
CAN
Bit 3:0 TS1[3:0] Time Segment 1
These bits define the number of time quanta in
Time Segment 1
t
= t
x (TS1[3:0] + 1)
BS1
CAN
.For more information on bit timing, please refer to
Section 10.10.5.7 Bit Timing.
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STMICROELECTRONICS [ ST ]
