CONTROLLER AREA NETWORK (bxCAN)
CONTROLLER AREA NETWORK (Cont’d)
Bit 4 = TXOK0 Transmission OK for mailbox 0
- Read
This bit is set by hardware when the transmission
request on mailbox 0 has been completed suc-
cessfully. Please refer to Figure 147.
Bit 6 = LOW1 Lowest Priority Flag for Mailbox 1
- Read
This bit is set by hardware when more than one
mailbox are pending for transmission and mailbox
1 has the lowest priority.
This bit is cleared by hardware when mailbox 0 is
requested for transmission or when the software
clears the RQCP0 bit.
Bit 5 = LOW0 Lowest Priority Flag for Mailbox 0
- Read
This bit is set by hardware when more than one
mailbox are pending for transmission and mailbox
0 has the lowest priority.
Bit 3 = Reserved. Forced to 0 by hardware.
Bit 2 = RQCP2 Request Completed for Mailbox 2
- Read/Clear
This bit is set by hardware to signal that the last re-
quest for mailbox 2 has been completed. The re-
quest could be a transmit or an abort request.
Note: These bits are set to zero when only one
mailbox is pending.
Bit 4 = TME2 Transmit Mailbox 2 Empty
- Read
This bit is set by hardware when no transmit re-
quest is pending for mailbox 2.
This bit is cleared by software.
Bit 1 = RQCP1 Request Completed for Mailbox 1
- Read/Clear
This bit is set by hardware to signal that the last re-
quest for mailbox 1 has been completed. The re-
quest could be a transmit or an abort request.
Bit 3 = TME1 Transmit Mailbox 1 Empty
- Read
This bit is set by hardware when no transmit re-
quest is pending for mailbox 1.
This bit is cleared by software.
Bit 2 = TME0 Transmit Mailbox 0 Empty
- Read
This bit is set by hardware when no transmit re-
quest is pending for mailbox 0.
Bit 0 = RQCP0 Request Completed for Mailbox 0
- Read/Clear
This bit is set by hardware to signal that the last re-
quest for mailbox 0 has been completed. The re-
quest could be a transmit or an abort request.
Bit 1:0 = CODE[1:0] Mailbox Code
- Read
This bit is cleared by software.
In case at least one transmit mailbox is free, the
code value is equal to the number of the next
transmit mailbox free.
CAN TRANSMIT PRIORITY REGISTER (CTPR)
All bits of this register are read only.
In case all transmit mailboxes are pending, the
code value is equal to the number of the transmit
mailbox with the lowest priority.
Reset Value: 0000 0000 (00h)
7
0
LOW2
LOW1
LOW0
TME2
TME1
TME0 CODE1 CODE0
Bit 7 = LOW2 Lowest Priority Flag for Mailbox 2
- Read
This bit is set by hardware when more than one
mailbox are pending for transmission and mailbox
2 has the lowest priority.
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STMICROELECTRONICS [ ST ]
