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ST10F276S-4T3 参数 Datasheet PDF下载

ST10F276S-4T3图片预览
型号: ST10F276S-4T3
PDF下载: 下载PDF文件 查看货源
内容描述: 16位MCU与MAC单元832 KB的闪存和68 KB的RAM [16-bit MCU with MAC unit 832 Kbyte Flash memory and 68 Kbyte RAM]
分类和应用: 闪存
文件页数/大小: 235 页 / 2491 K
品牌: STMICROELECTRONICS [ ST ]
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Internal Flash memory  
ST10F276E  
Table 4.  
Bank  
Flash modules sectorization (write operations or with ROMS1 = ‘1’)  
ST10 Bus  
size  
Description  
Addresses  
Size  
Bank 0 Test-Flash (B0TF)  
Bank 0 Flash 0 (B0F0)  
Bank 0 Flash 1 (B0F1)  
Bank 0 Flash 2 (B0F2)  
Bank 0 Flash 3 (B0F3)  
Bank 0 Flash 4 (B0F4)  
Bank 0 Flash 5 (B0F5)  
Bank 0 Flash 6 (B0F6)  
Bank 0 Flash 7 (B0F7)  
Bank 0 Flash 8 (B0F8)  
Bank 0 Flash 9 (B0F9)  
Bank 1 Flash 0 (B1F0)  
Bank 1 Flash 1 (B1F1)  
Bank 2 Flash 0 (B2F0)  
Bank 2 Flash 1 (B2F1)  
Bank 2 Flash 2 (B2F2)  
Bank 3 Flash 0 (B3F0)  
Bank 3 Flash 1 (B3F1)  
0x0000 0000 - 0x0000 1FFF  
0x0001 0000 - 0x0001 1FFF  
0x0001 2000 - 0x0001 3FFF  
0x0001 4000 - 0x0001 5FFF  
0x0001 6000 - 0x0001 7FFF  
0x0001 8000 - 0x0001 FFFF  
0x0002 0000 - 0x0002 FFFF  
0x0003 0000 - 0x0003 FFFF  
0x0004 0000 - 0x0004 FFFF  
0x0005 0000 - 0x0005 FFFF  
0x0006 0000 - 0x0006 FFFF  
0x0007 0000 - 0x0007 FFFF  
0x0008 0000 - 0x0008 FFFF  
0x0009 0000 - 0x0009 FFFF  
0x000A 0000 - 0x000A FFFF  
0x000B 0000 - 0x000B FFFF  
0x000C 0000 - 0x000C FFFF  
0x000D 0000 - 0x000D FFFF  
8 KB  
8 KB  
8 KB  
8 KB  
8 KB  
32 KB  
B0  
64 KB 32-bit (I-BUS)  
64 KB  
64 KB  
64 KB  
64 KB  
64 KB  
B1  
B2  
B3  
64 KB  
64 KB  
64 KB  
16-bit  
(X-BUS)  
64 KB  
64 KB  
64 KB  
Table 4 above refers to the configuration when bit ROMS1 of SYSCON register is set. When  
Bootstrap mode is entered:  
Test-Flash is seen and available for code fetches (address 00’0000h)  
User IFlash is only available for read and write accesses  
Write accesses must be made with addresses starting in segment 1 from 01'0000h,  
whatever ROMS1 bit in SYSCON value  
Read accesses are made in segment 0 or in segment 1 depending of ROMS1 value.  
In Bootstrap mode, by default ROMS1 = 0, so the first 32 Kbytes of IFlash are mapped in  
segment 0.  
Example: In default configuration, to program address 0, user must put the value 01'0000h  
in the FARL and FARH registers, but to verify the content of the address 0 a read to  
00'0000h must be performed.  
Table 5 shows the control register interface composition: this set of registers can be  
addressed by the CPU.  
26/235  
Doc ID 12303 Rev 3  
 
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