A d v a n c e I n f o r m a t i o n
Table 6. 32- Bit Linear and Burst Data Order
Data Transfer Sequence
(Independent of the WORD#
pin)
Output Data Sequence (Initial Access Address)
(x16)
0-1 (A0 = 0)
1-0 (A0 = 1)
Two Linear Data Transfers,
0-1-2-3 (A0:A-1/A1-A0 = 00)
1-2-3-0 (A0:A-1/A1-A0 = 01)
2-3-0-1 (A:A-1/A1-A0 = 10)
3-0-1-2 (A0:A-1/A1-A0 = 11)
Four Linear Data Transfers
0-1-2-3-4-5-6-7 (A1:A-1A2-A0 = 000)
1-2-3-4-5-6-7-0 (A1:A-1/A2-A0 = 001)
2-3-4-5-6-7-0-1 (A1:A-1/A2-A0 = 010)
3-4-5-6-7-0-1-2 (A1:A-1/A2-A0 = 011)
4-5-6-7-0-1-2-3 (A1:A-1/A2-A0 = 100)
5-6-7-0-1-2-3-4 (A1:A-1/A2-A0 = 101)
6-7-0-1-2-3-4-5 (A1:A-1/A2-A0 = 110)
7-0-1-2-3-4-5-6 (A1:A-1/A2-A0 = 111)
Eight Linear Data Transfers
March 22, 2004 30606B0
S29CD032G
21
SPANSION [ SPANSION ]
