CXD1968AR
AGC_MANUAL_1
Read/Write
RESET: 0x00
Default R/W
Offset Address: 0x06
Bit
Name
Description
7:0 AGC Manual
AGC manual setting bits 7:0
00h
R/W
AGC_MANUAL_2
Read/Write
RESET: 0x00
Default R/W
Offset Address: 0x07
Bit
Name
Description
7:4 Reserved
0000
0000
R/W
R/W
3:0 AGC Manual
AGC manual setting bits 11:8
Note) 1. In the time interval between host writes to AGC_MANUAL_1 and AGC_MANUAL_2, the manual
control to the AGC will have an intermediate value.
2. AGC Manual has been extended by 2 bits for the CXD1968AR and CXD1976R compared to the
CXD1973Q. AGC_MANUAL_2[3:2] were previously reserved bits that are now used for this
purpose.
3. AGC_MANUAL is a 2’s compliment value.
AGC_TARGET
Read/Write
RESET: 0x28
Default R/W
Offset Address: 0x08
Bit
Name
Description
AGC target bits 7:0. This register sets the base AGC target level.
7:0 AGC Target
28h
R/W
Note) The default value will give 12.5dB headroom with 1Vp-p ADC input range for gaussian signals.
AGC_GAIN_1
Read Only
Offset Address: 0x09
Bit
Name
Description
Default R/W
R/W
7:0 AGC Gain I
Current (or latched) AGC gain bits 7:0
—
AGC_GAIN_2
Read/Write
RESET: 0x00
Offset Address: 0x0A
Bit
7
Name
Description
Default R/W
If set, the input signal to AGC is a DC-free signal, provided
DCC is enabled.
AGC_AFTER_DCC
0
R/W
6
5
4
LOCK_Q
LOCK_I
AGC locked indication on the Q channel
AGC locked indication on the I channel
AGC locked indication
0
0
0
0
R
R
R
R
AGC Locked
3:0 AGC Gain I
Current (or latched) AGC gain bits 11:8
Note) 1. AGC gain is the AGC value in normal operation, but is NOT influenced by AGC_CTL (AGC Set).
Refer to PIR_CTL register description for details of the latched mode.
2. The AGC gain range read back is –2048 to +2047.
3. AGC Gain has been extended by 2 bits for the CXD1968AR and CXD1976R compared to the
CXD1973Q. AGC_GAIN_2[3:2] were previously reserved bits that are now used for this purpose.
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SONY [ SONY CORPORATION ]
